Wenliang Tseng

	2006
2		Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su: Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Transactions 89-C(11): 1713-1718 (2006)
	2001
1		Chauchin Su, Wenliang Tseng: Configuration free SoC interconnect BIST methodology. ITC 2001: 1033-1038

Coauthor Index

1	Chien-Nan Jimmy Liu	[2]
2	Chauchin Su	[1] [2]