Akira Tsuchiya

	2009
16		Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng: High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390
15		Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera: Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED 2009: 195-200
	2008
14		Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera: Statistical gate delay model for Multiple Input Switching. ASP-DAC 2008: 286-291
13		Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng: On-chip high performance signaling using passive compensation. ICCD 2008: 182-187
12		Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng: Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Transactions 91-A(12): 3474-3480 (2008)
	2007
11		Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera: A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. ASP-DAC 2007: 120-121
10		Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera: Worst-case delay analysis considering the variability of transistors and interconnects. ISPD 2007: 35-42
9		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Transactions 90-C(6): 1267-1273 (2007)
8		Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera: Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Transactions 90-C(6): 1274-1281 (2007)
	2006
7		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL extraction at a single representative frequency. ASP-DAC 2006: 515-520
6		Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto: Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Transactions 89-A(12): 3560-3568 (2006)
5		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Transactions 89-A(12): 3585-3593 (2006)
4		Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera: Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Transactions 89-C(3): 327-333 (2006)
	2005
3		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Return path selection for loop RL extraction. ASP-DAC 2005: 1078-1081
2		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Transactions 88-A(4): 885-891 (2005)
	2004
1		Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera: Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC 2004: 691-696

Coauthor Index

1	Chung-Kuan Cheng	[12] [13] [16]
2	Takayuki Fukuoka	[10] [14]
3	Masanori Hashimoto	[1] [2] [3] [5] [6] [7] [9] [12] [13] [16]
4	Tatsuhiko Ikeda	[6]
5	Toshiki Kanamoto	[6]
6	Kazutoshi Kobayashi	[4] [15]
7	Takeshi Kuboki	[8] [11]
8	Ernest S. Kuh	[16]
9	Hidetoshi Onodera	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [14] [15]
10	Jangsombatsiri Siriporn	[12]
11	Hiroki Sunagawa	[15]
12	Haruhiko Terada	[15]
13	Yoichi Yuyama	[4]
14	Ling Zhang	[13] [16]
15	Yulei Zhang	[13] [16]
16	Haikun Zhu	[12]