 | 2009 |
|---|
| 9 |       | Vu Manh Tuan,
Naohiro Katsura,
Hiroki Matsutani,
Hideharu Amano:
Evaluation of a multicore reconfigurable architecture with variable core sizes.
IPDPS 2009: 1-8 |
| 2008 |
|---|
| 8 | | Vu Manh Tuan,
Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.
ARC 2008: 171-182 |
| 7 |  | Vu Manh Tuan,
Hideharu Amano:
A Method for Capturing State Data on Dynamically Reconfigurable Processors.
ERSA 2008: 208-214 |
| 6 | | Vu Manh Tuan,
Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors.
IEICE Transactions 91-D(12): 2793-2803 (2008) |
| 5 | | Vu Manh Tuan,
Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors.
IEICE Transactions 91-D(9): 2312-2322 (2008) |
| 2007 |
|---|
| 4 | | Vu Manh Tuan,
Yohei Hasegawa,
Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor.
ERSA 2007: 203-206 |
| 2006 |
|---|
| 3 | | Vu Manh Tuan,
Yohei Hasegawa,
Naohiro Katsura,
Hideharu Amano:
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor.
ARC 2006: 115-121 |
| 2 | | Masayasu Suzuki,
Yohei Hasegawa,
Vu Manh Tuan,
Shohei Abe,
Hideharu Amano:
A cost-effective context memory structure for dynamically reconfigurable processors.
IPDPS 2006 |
| 1 | | Yohei Hasegawa,
Shohei Abe,
Shunsuke Kurotaki,
Vu Manh Tuan,
Naohiro Katsura,
Takuro Nakamura,
Takashi Nishimura,
Hideharu Amano:
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor.
IPDPS 2006 |
