| 2009 | ||
|---|---|---|
| 77 | Leo Porter, Dean M. Tullsen: Creating artificial global history to improve branch prediction accuracy. ICS 2009: 266-275 | |
| 76 | Leo Porter, Bumyong Choi, Dean M. Tullsen: Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading. PACT 2009: 313-324 | |
| 75 | Ayse Kivilcim Coskun, Richard Strong, Dean M. Tullsen, Tajana Simunic Rosing: Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. SIGMETRICS/Performance 2009: 169-180 | |
| 74 | Joel S. Emer, Dean M. Tullsen: Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences. IEEE Micro 29(1): 6-9 (2009) | |
| 73 | Richard Strong, Jayaram Mudigonda, Jeffrey C. Mogul, Nathan L. Binkert, Dean M. Tullsen: Fast switching of threads between cores. Operating Systems Review 43(2): 35-45 (2009) | |
| 2008 | ||
| 72 | Bumyong Choi, Leo Porter, Dean M. Tullsen: Accurate branch prediction for short threads. ASPLOS 2008: 125-134 | |
| 71 | Subhradyuti Sarkar, Dean M. Tullsen: Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture. HiPEAC 2008: 353-368 | |
| 70 | Jeffery A. Brown, Dean M. Tullsen: The shared-thread multiprocessor. ICS 2008: 73-82 | |
| 69 | Dean M. Tullsen: Holistic Design of Multiple-Core Architectures. ISPDC 2008: 8-9 | |
| 68 | Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen: Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distrib. Syst. 19(7): 914-925 (2008) | |
| 67 | Brad Calder, Dean M. Tullsen: Editorial. TACO 5(1): (2008) | |
| 2007 | ||
| 66 | Dean M. Tullsen, Brad Calder: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA ACM 2007 | |
| 65 | Weifeng Zhang, Dean M. Tullsen, Brad Calder: Accelerating and Adapting Precomputation Threads for Effcient Prefetching. HPCA 2007: 85-95 | |
| 64 | Dean M. Tullsen: HCW Keynote Address Holistic Design of Multi-Core Architectures. IPDPS 2007: 1 | |
| 63 | Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen: Proximity-aware directory-based coherence for multi-core processor architectures. SPAA 2007: 126-134 | |
| 62 | Rakesh Kumar, Dean M. Tullsen: The architecture of Efficient Multi-Core Processors: A Holistic Approach. Advances in Computers 69: 1-87 (2007) | |
| 61 | Ravi Iyer, Dean M. Tullsen: Editorial: Special Section on CMP Architectures. IEEE Trans. Parallel Distrib. Syst. 18(8): 1025-1027 (2007) | |
| 60 | Brad Calder, Dean M. Tullsen: Introduction. TACO 4(1): (2007) | |
| 2006 | ||
| 59 | Weifeng Zhang, Brad Calder, Dean M. Tullsen: A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework. CGO 2006: 50-64 | |
| 58 | David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen: Application-specific customization of parameterized FPGA soft-core processors. ICCAD 2006: 261-268 | |
| 57 | David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky: Conjoining soft-core FPGA processors. ICCAD 2006: 694-701 | |
| 56 | Weifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway: Speculative Code Value Specialization Using the Trace Cache Fill Unit. ICCD 2006 | |
| 55 | M. De Vuyst, Rakesh Kumar, Dean M. Tullsen: Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors. IPDPS 2006 | |
| 54 | Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi: Core architecture optimization for heterogeneous chip multiprocessors. PACT 2006: 23-32 | |
| 53 | Brad Calder, Dean M. Tullsen: Introduction. TACO 3(1): 1-2 (2006) | |
| 2005 | ||
| 52 | Nathan Tuck, Dean M. Tullsen: Multithreaded Value Prediction. HPCA 2005: 5-15 | |
| 51 | Weifeng Zhang, Brad Calder, Dean M. Tullsen: An Event-Driven Multithreaded Dynamic Optimization Framework. IEEE PACT 2005: 87-98 | |
| 50 | Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh: A Tree Based Router Search Engine Architecture with Single Port Memories. ISCA 2005: 123-133 | |
| 49 | Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen: Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA 2005: 408-419 | |
| 48 | Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen: Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. PLDI 2005: 269-279 | |
| 47 | Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou: The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. Computer Architecture Letters 4(1): 1 (2005) | |
| 46 | Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan: Heterogeneous Chip Multiprocessors. IEEE Computer 38(11): 32-38 (2005) | |
| 45 | Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen: Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). SIGARCH Computer Architecture News 33(4): 4 (2005) | |
| 44 | Brad Calder, Dean M. Tullsen: Introduction. TACO 2(1): 1-2 (2005) | |
| 2004 | ||
| 43 | Jamison D. Collins, Dean M. Tullsen: Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time. IPDPS 2004 | |
| 42 | Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas: Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA 2004: 64-75 | |
| 41 | Jamison D. Collins, Dean M. Tullsen, Hong Wang: Control Flow Optimization Via Dynamic Reconvergence Prediction. MICRO 2004: 129-140 | |
| 40 | Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder: Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. MICRO 2004: 183-194 | |
| 39 | Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen: Conjoined-Core Chip Multiprocessing. MICRO 2004: 195-206 | |
| 38 | Brad Calder, Dean M. Tullsen: Introduction. TACO 1(1): 1-2 (2004) | |
| 2003 | ||
| 37 | Nathan Tuck, Dean M. Tullsen: Initial Observations of the Simultaneous Multithreading Pentium 4 Processor. IEEE PACT 2003: 26- | |
| 36 | John S. Seng, Dean M. Tullsen: The Effect of Compiler Optimizations on Pentium 4 Power Consumption. Interaction between Compilers and Computer Architectures 2003: 51-56 | |
| 35 | Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen: Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. MICRO 2003: 81-92 | |
| 34 | John S. Seng, Dean M. Tullsen: Exploring the Potential of Architecture-Level Power Optimizations. PACS 2003: 132-147 | |
| 33 | Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen: Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. Computer Architecture Letters 2: (2003) | |
| 2002 | ||
| 32 | Eric Tune, Dean M. Tullsen, Brad Calder: Quantifying Instruction Criticality. IEEE PACT 2002: 104- | |
| 31 | Rakesh Kumar, Dean M. Tullsen: Compiling for instruction cache performance on a multithreaded architecture. MICRO 2002: 419-429 | |
| 30 | Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen: Pointer cache assisted prefetching. MICRO 2002: 62-73 | |
| 29 | Allan Snavely, Dean M. Tullsen, Geoffrey M. Voelker: Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. SIGMETRICS 2002: 66-76 | |
| 2001 | ||
| 28 | Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder: Dynamic Prediction of Critical Path Instructions. HPCA 2001: 185-196 | |
| 27 | Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen: Speculative precomputation: long-range prefetching of delinquent loads. ISCA 2001: 14-25 | |
| 26 | John S. Seng, Eric Tune, Dean M. Tullsen: Reducing power with dynamic critical path information. MICRO 2001: 114-123 | |
| 25 | Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen: Dynamic speculative precomputation. MICRO 2001: 306-317 | |
| 24 | Dean M. Tullsen, Jeffery A. Brown: Handling long-latency loads in a simultaneous multithreading processor. MICRO 2001: 318-327 | |
| 23 | Jamison D. Collins, Dean M. Tullsen: Runtime identification of cache conflict misses: The adaptive miss buffer. ACM Trans. Comput. Syst. 19(4): 413-439 (2001) | |
| 2000 | ||
| 22 | Allan Snavely, Dean M. Tullsen: Symbiotic Jobscheduling for a Simultaneous Multithreading Processor. ASPLOS 2000: 234-244 | |
| 21 | John S. Seng, Dean M. Tullsen, George Cai: Power-Sensitive Multithreaded Architecture. ICCD 2000: 199- | |
| 20 | Barbara Kreaseck, Dean M. Tullsen, Brad Calder: Limits of Task-Based Parallelism in Irregular Applications. ISHPC 2000: 43-58 | |
| 1999 | ||
| 19 | Dean M. Tullsen, Guang R. Gao: Multithreaded Execution Architecture and Compilation. HPCA 1999: 321 | |
| 18 | Steven Wallace, Dean M. Tullsen, Brad Calder: Instruction Recycling on a Multiple-Path Processor. HPCA 1999: 44-53 | |
| 17 | Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy: Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor. HPCA 1999: 54-58 | |
| 16 | Dean M. Tullsen, John S. Seng: Storageless Value Prediction Using Prior Register Values. ISCA 1999: 270-279 | |
| 15 | Brad Calder, Glenn Reinman, Dean M. Tullsen: Selective Value Prediction. ISCA 1999: 64-74 | |
| 14 | Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin: Classifying load and store instructions for memory renaming. International Conference on Supercomputing 1999: 399-407 | |
| 13 | Jamison D. Collins, Dean M. Tullsen: Hardware Identification of Cache Conflict Misses. MICRO 1999: 126-135 | |
| 12 | Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen: Software-Directed Register Deallocation for Simultaneous Multithreaded Processors. IEEE Trans. Parallel Distrib. Syst. 10(9): 922-933 (1999) | |
| 11 | Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen: Tuning Compiler Optimizations for Simultaneous Multithreading. International Journal of Parallel Programming 27(6): 477-503 (1999) | |
| 1998 | ||
| 10 | Dean M. Tullsen, Susan J. Eggers, Henry M. Levy: Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism. 25 Years ISCA: Retrospectives and Reprints 1998: 115-116 | |
| 9 | Dean M. Tullsen, Susan J. Eggers, Henry M. Levy: Simultaneous Multithreading: Maximizing On-Chip Parallelism. 25 Years ISCA: Retrospectives and Reprints 1998: 533-544 | |
| 8 | Steven Wallace, Brad Calder, Dean M. Tullsen: Threaded Multiple Path Execution. ISCA 1998: 238-249 | |
| 1997 | ||
| 7 | Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen: Tuning Compiler Optimizations for Simultaneous Multithreading. MICRO 1997: 114-124 | |
| 6 | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen: Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ACM Trans. Comput. Syst. 15(3): 322-354 (1997) | |
| 1996 | ||
| 5 | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ISCA 1996: 191-202 | |
| 4 | Dean M. Tullsen: Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor. Int. CMG Conference 1996: 819-828 | |
| 1995 | ||
| 3 | Dean M. Tullsen, Susan J. Eggers, Henry M. Levy: Simultaneous Multithreading: Maximizing On-Chip Parallelism. ISCA 1995: 392-403 | |
| 2 | Dean M. Tullsen, Susan J. Eggers: Effective Cache Prefetching on Bus-Based Multiprocessors ACM Trans. Comput. Syst. 13(1): 57-88 (1995) | |
| 1993 | ||
| 1 | Dean M. Tullsen, Susan J. Eggers: Limitations of Cache Prefetching on a Bus-Based Multiprocessor. ISCA 1993: 278-288 | |