 | 2006 |
|---|
| 12 |       | Dan Cyca,
Laurence E. Turner:
Bit-Serial Digital Filter Implementation using a Custom C Compiler.
APCCAS 2006: 534-537 |
| 2004 |
|---|
| 11 |  | Sean E. Krakiwsky,
Laurence E. Turner,
Michal M. Okoniewski:
Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm.
ISCAS (5) 2004: 265-268 |
| 10 | | S. A. Rahim,
Laurence E. Turner:
A Field Programmable Bit-Serial Digital Signal Processor.
IWSOC 2004: 295-298 |
| 2002 |
|---|
| 9 | | Ryan N. Schneider,
Laurence E. Turner,
Michal M. Okoniewski:
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method.
FPGA 2002: 97-105 |
| 8 | | Trevor W. Fox,
Laurence E. Turner:
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA.
FPL 2002: 492-502 |
| 7 | | S. G. Gibb,
Laurence E. Turner:
The Automatic Generation of Application Specific Processors.
IWLS 2002: 161-165 |
| 1997 |
|---|
| 6 | | T. Mathews,
S. G. Gibb,
Laurence E. Turner,
Peter J. W. Graumann,
M. Fattouche:
An FPGA implementation of a matched filter detector for spread spectrum communications systems.
FPL 1997: 364-373 |
| 1995 |
|---|
| 5 | | Laurence E. Turner,
Peter J. W. Graumann:
Rapid Hardware Prototyping of Digital Signal Processing Systems Using FPGAs.
FPL 1995: 129-138 |
| 4 | | G. Panneerselvam,
Peter J. W. Graumann,
Laurence E. Turner:
Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs.
FPL 1995: 272-281 |
| 3 | | Laurence E. Turner,
Peter J. W. Graumann,
S. G. Gibb:
BIT-Serial FIR Filters with CSD Coefficients for FPGAs.
FPL 1995: 311-320 |
| 1994 |
|---|
| 2 | | Bruce A. Johnston,
Peter J. W. Graumann,
Laurence E. Turner:
DSP System Synthesis Including Variable Data Path Width.
ISCAS 1994: 53-56 |
| 1991 |
|---|
| 1 | | R. Nagalla,
Laurence E. Turner:
Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms.
VLSI 1991: 39-48 |
