Sergey Tverdyshev

	2009
4		Mark A. Hillebrand, Sergey Tverdyshev: Formal Verification of Gate-Level Computer Systems. CSR 2009: 322-333
	2008
3		Sergey Tverdyshev, Eyad Alkassar: Efficient Bit-Level Model Reductions for Automated Hardware Verification. TIME 2008: 164-172
	2007
2		Eyad Alkassar, Mark A. Hillebrand, Steffen Knapp, Rostislav Rusev, Sergey Tverdyshev: Formal Device and Programming Model for a Serial Interface. VERIFY 2007
	2005
1		Sergey Tverdyshev: Combination of Isabelle/HOL with Automatic Tools. FroCos 2005: 302-309

Coauthor Index

1	Eyad Alkassar	[2] [3]
2	Mark A. Hillebrand	[2] [4]
3	Steffen Knapp	[2]
4	Rostislav Rusev	[2]