Gary S. Tyson

	2009
49		Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee: Core monitors: monitoring performance in multicore processors. Conf. Computing Frontiers 2009: 31-40
48		Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson: Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). LCTES 2009: 119-128
47		Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson: Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. T. HiPEAC 2: 65-84 (2009)
46		Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: Practical exhaustive optimization phase order exploration and evaluation. TACO 6(1): (2009)
	2008
45		Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy K. John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson: Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education. CollaborateCom 2008: 70-84
44		David B. Whalley, Gary S. Tyson: Enhancing the effectiveness of utilizing an instruction register file. IPDPS 2008: 1-5
43		Renato J. O. Figueiredo, P. Oscar Boykin, José A. B. Fortes, Tao Li, Jie-Kwon Peir, David Wolinsky, Lizy Kurian John, David R. Kaeli, David J. Lilja, Sally A. McKee, Gokhan Memik, Alain Roy, Gary S. Tyson: Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education CoRR abs/0807.1765: (2008)
	2007
42		Chris Zimmer, Stephen Roderick Hines, Prasad Kulkarni, Gary S. Tyson, David B. Whalley: Facilitating compiler optimizations through the dynamic mapping of alternate register structures. CASES 2007: 165-169
41		Prasad Kulkarni, David B. Whalley, Gary S. Tyson: Evaluating Heuristic Optimization Phase Order Search Algorithms. CGO 2007: 157-169
40		Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson: Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. HiPEAC 2007: 23-37
39		Stephen Roderick Hines, Gary S. Tyson, David B. Whalley: Addressing instruction fetch bottlenecks by using an instruction register file. LCTES 2007: 165-174
38		Stephen Hines, David B. Whalley, Gary S. Tyson: Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. MICRO 2007: 433-444
37		Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems. T. HiPEAC 1: 54-73 (2007)
	2006
36		Stephen Hines, David B. Whalley, Gary S. Tyson: Adapting compilation techniques to enhance the packing of instructions into registers. CASES 2006: 43-53
35		Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: Exhaustive Optimization Phase Order Space Exploration. CGO 2006: 306-318
34		William C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson: Reducing the cost of conditional transfers of control by using comparison specifications. LCTES 2006: 64-71
33		Prasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson: In search of near-optimal optimization phase orderings. LCTES 2006: 83-92
32		Allen C. Cheng, Gary S. Tyson: High-quality ISA synthesis for low-power cache designs in embedded microprocessors. IBM Journal of Research and Development 50(2-3): 299-310 (2006)
	2005
31		Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Drowsy region-based caches: minimizing both dynamic and static power dissipation. Conf. Computing Frontiers 2005: 378-384
30		Michael J. Geiger, Sally A. McKee, Gary S. Tyson: Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. HiPEAC 2005: 102-115
29		Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley: Improving Program Efficiency by Packing Instructions into Registers. ISCA 2005: 260-271
28		Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge: PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis. ISPASS 2005: 32-41
27		Stephen Hines, Gary S. Tyson, David B. Whalley: Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. MICRO 2005: 19-29
26		Allen C. Cheng, Gary S. Tyson: An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. IEEE Trans. Computers 54(6): 698-713 (2005)
	2004
25		Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors. DAC 2004: 920-923
24		Viji Srinivasan, Edward S. Davidson, Gary S. Tyson: A Prefetch Taxonomy. IEEE Trans. Computers 53(2): 126-140 (2004)
	2001
23		Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak: Branch History Guided Instruction Prefetching. HPCA 2001: 291-300
22		Hsien-Hsin S. Lee, Mikhail Smelyanskiy, Chris J. Newburn, Gary S. Tyson: Stack Value File: Custom Microarchitecture for the Stack. HPCA 2001: 5-14
21		Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson: Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD 2001: 133-141
20		Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens: Improving Bandwidth Utilization using Eager Writeback. J. Instruction-Level Parallelism 3: (2001)
	2000
19		Hsien-Hsin S. Lee, Gary S. Tyson: Region-based caching: an energy-delay efficient memory architecture for embedded processors. CASES 2000: 120-127
18		Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson: Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT 2000: 3-12
17		Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens: Eager writeback - a technique for improving bandwidth utilization. MICRO 2000: 11-21
16		Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson: Improving BTB performance in the presence of DLLs. MICRO 2000: 77-86
	1999
15		Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin: Classifying load and store instructions for memory renaming. International Conference on Supercomputing 1999: 399-407
14		Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999)
13		Gary S. Tyson, Todd M. Austin: Memory Renaming: Fast, Early and Accurate Processing of Memory Communication. International Journal of Parallel Programming 27(5): 357-380 (1999)
12		Matt Postiff, Gary S. Tyson, Trevor N. Mudge: Performance Limits of Trace Caches. J. Instruction-Level Parallelism 1: (1999)
	1998
11		Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens: Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456
10		Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson: mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26
9		Sangwook P. Kim, Gary S. Tyson: Analyzing the Working Set Characteristics of Branch Execution. MICRO 1998: 49-58
	1997
8		Gary S. Tyson, Todd M. Austin: Improving the Accuracy and Performance of Memory Communication Through Renaming. MICRO 1997: 218-227
7		Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56
	1995
6		Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun: A modified approach to data cache management. MICRO 1995: 93-103
	1994
5		Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun: A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347
4		Gary S. Tyson: The effects of predicated execution on branch prediction. MICRO 1994: 196-206
	1993
3		Gary S. Tyson, Matthew K. Farrens: Techniques for extracting instruction level parallelism on MIMD architectures. MICRO 1993: 128-137
	1992
2		Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun: MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196
1		Matthew K. Farrens, Arvin Park, Gary S. Tyson: Modifying VM hardware to reduce address pin requirements. MICRO 1992: 210-213

Coauthor Index

1	Todd M. Austin	[7] [8] [13] [15]
2	Major Bhadauria	[40] [47]
3	P. Oscar Boykin	[43] [45]
4	Brad Calder	[15]
5	Mark J. Charney	[23]
6	Allen C. Cheng	[25] [26] [28] [32]
7	Edward S. Davidson	[7] [10] [11] [14] [16] [18] [21] [23] [24]
8	Jack W. Davidson	[33] [35] [46]
9	Matthew K. Farrens	[1] [2] [3] [5] [6] [11] [17] [20]
10	Renato J. O. Figueiredo	[43] [45]
11	José A. B. Fortes	[43] [45]
12	Peter Gavin	[48]
13	Michael J. Geiger	[30] [31] [37]
14	Joshua Green	[29]
15	Stephen Roderick Hines (Stephen Hines)	[27] [29] [34] [36] [38] [39] [42] [48]
16	Lizy Kurian John (Lizy K. John)	[43] [45]
17	David R. Kaeli	[43] [45]
18	Sangwook P. Kim	[9]
19	William C. Kreahling	[34]
20	Prasad Kulkarni	[33] [35] [41] [42] [46]
21	Hsien-Hsin S. Lee	[17] [19] [20] [22]
22	Tao Li	[43] [45]
23	David J. Lilja	[43] [45]
24	John Matthews	[6]
25	Sally A. McKee	[30] [31] [37] [40] [43] [45] [47] [49]
26	Gokhan Memik	[43] [45]
27	Trevor N. Mudge	[12] [25] [28]
28	Chris J. Newburn	[22]
29	Arvin Park	[1]
30	Jie-Kwon Peir	[43] [45]
31	Yuval Peress	[48] [49]
32	Andrew R. Pleszkun	[2] [5] [6]
33	Matt Postiff	[12]
34	Thomas R. Puzak	[23]
35	Glenn Reinman	[15]
36	Jude A. Rivers	[7] [10] [11] [14]
37	Alain J. Roy (Alain Roy)	[43] [45]
38	Karan Singh	[40] [47]
39	Mikhail Smelyanskiy	[18] [22]
40	Vijayalakshmi Srinivasan	[14]
41	Viji Srinivasan	[23] [24]
42	Edward S. Tam	[10] [11] [14] [21]
43	Dean M. Tullsen	[15]
44	Stevan A. Vlaovic	[16] [21]
45	Paul E. West	[49]
46	David B. Whalley	[27] [29] [33] [34] [35] [36] [38] [39] [41] [42] [44] [46] [48]
47	David Wolinsky (David Isaac Wolinsky)	[43] [45]
48	Chris Zimmer	[42]

Colors in the list of coauthors