Kaname Uchikura

	2006
5		Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo: A Model of Implementable SMT Processor on FPGA. PDPTA 2006: 909-915
4		Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo: Towards Reconfigurable Cache Memory for a Multithreaded Processor. PDPTA 2006: 916-924
	2005
3		Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. PDPTA 2005: 447-453
2		Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki: Development of a Thread Scheduler for SMT Processor Architecture. PDPTA 2005: 454-460
	2004
1		Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo: Dynamic Allocation of Physical Register Banks for an SMT Processor. PDPTA 2004: 317-323

Coauthor Index

1	Kazunari Asano	[4] [5]
2	Norito Kato	[1] [2] [3]
3	Hironori Nakajo	[1] [2] [3] [4] [5]
4	Mitaro Namiki	[1] [2] [3] [4] [5]
5	Yoshiyasu Ogasawara	[3] [4] [5]
6	Koichi Sasada	[1] [2] [3] [4] [5]
7	Mikiko Sato	[1] [2] [3] [4] [5]
8	Ippei Tate	[4] [5]
9	Osamu Tujimoto	[1]
10	Satoshi Watanabe	[4] [5]
11	Masanori Yamato	[1] [2] [3]