Takumi Uezono

	2009
13		Takumi Uezono, Takashi Sato, Kazuya Masu: One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Transactions 92-A(4): 1024-1030 (2009)
	2008
12		Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Transactions 91-A(4): 951-956 (2008)
	2007
11		Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI 2007: 513-516
10		Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu: A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED 2007: 21-26
9		Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu: Weakness Identification for Effective Repair of Power Distribution Network. PATMOS 2007: 222-231
8		Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu: Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8
	2006
7		Takumi Uezono, Kenichi Okada, Kazuya Masu: Via Distribution Model for Yield Estimation. ISQED 2006: 479-484
6		Kenichi Okada, Takumi Uezono, Kazuya Masu: Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. PATMOS 2006: 181-190
5		Takumi Uezono, Kenichi Okada, Kazuya Masu: Statistical Modeling of a Via Distribution for Yield Estimation. IEICE Transactions 89-A(12): 3579-3584 (2006)
	2005
4		Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu: Evaluation of on-chip transmission line interconnect using wire length distribution. ASP-DAC 2005: 133-138
3		Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model Considering Core Utilization for System on Chip. ISVLSI 2005: 276-277
2		Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu: Prediction of delay time for future LSI using on-chip transmission line interconnects. SLIP 2005: 7-12
1		Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu: Wire Length Distribution Model for System LSI. IEICE Transactions 88-A(12): 3445-3452 (2005)

Coauthor Index

1	Shuhei Amakawa	[8] [10]
2	Shinichiro Gomi	[4]
3	Shiho Hagiwara	[9] [10] [11] [12]
4	Junpei Inoue	[1] [2] [3] [4]
5	Hiroyuki Ito	[4]
6	Takanori Kyogoku	[1] [2] [3] [4]
7	Kazuya Masu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
8	Hidenari Nakashima	[1] [3]
9	Noriaki Nakayama	[10]
10	Kenichi Okada	[1] [2] [3] [4] [5] [6] [7] [8] [10]
11	Takashi Sato	[8] [9] [10] [11] [12] [13]