 | 2005 |
|---|
| 4 |       | Ganesan Umanesan,
Eiji Fujiwara:
Parallel Decoding Cyclic Burst Error Correcting Codes.
IEEE Trans. Computers 54(1): 87-92 (2005) |
| 2003 |
|---|
| 3 | | Ganesan Umanesan,
Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes.
IEEE Trans. Computers 52(7): 835-847 (2003) |
| 2002 |
|---|
| 2 | | Ganesan Umanesan,
Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems.
PRDC 2002: 247-256 |
| 2000 |
|---|
| 1 | | Ganesan Umanesan,
Eiji Fujiwara:
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems.
DFT 2000: 192-200 |
