Sreehari Veeramachaneni

	2012
16		Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285
	2011
15		Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429
14		Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350
	2010
13		Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44
12		Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI 2010: 434-435
11		Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design 2010: 411-416
10		Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas: An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electronics 6(3): 429-435 (2010)
	2009
9		Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas: A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI 2009: 211-216
8		Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A novel low power, variable resolution pipelined ADC. SoCC 2009: 183-186
7		Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas: Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design 2009: 117-122
6		Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas: A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electronics 5(3): 279-290 (2009)
	2008
5		Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas: A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552
	2007
4		Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas: Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191
3		Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS 2007: 3271-3274
2		Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI 2007: 343-350
1		Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas: Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design 2007: 324-329

Coauthor Index

1	Mahesh Kumar Adimulam	[6] [7] [8] [11] [12] [13]
2	Syed Ershad Ahmed	[14] [15] [16]
3	Lingamneni Avinash	[1] [2] [3] [4]
4	Aman Gupta	[9]
5	Kirthi M. Krishna	[1] [2] [3] [4] [5]
6	A. Mahesh Kumar	[10]
7	Goutham Makkena	[16]
8	Krishna Kumar Movva	[13]
9	N. Moorthy Muthukrishnan	[12] [13] [14] [15] [16]
10	M. Venkata Swamy Nayudu	[16]
11	Sai Phaneendra P.	[14] [15] [16]
12	Bharat S.	[5]
13	Subroto S.	[5]
14	Sandeep Saini	[10] [11]
15	Anshul Singh	[9]
16	Reddy Puppala Sreekanth	[1] [2] [3]
17	M. B. Srinivas (Mandalika B. Srinivas)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
18	Venkat Tummala	[7]
19	Chetan Kumar V.	[14] [15]
20	Prateek G. V.	[5]
21	Chetan Vudadha	[16]

Last update Fri May 25 01:42:58 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page