 | 2009 |
|---|
| 88 |       | Gearold Johnson,
Carsten Trinitis,
Georgi Gaydadjiev,
Alexander V. Veidenbaum:
Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009
ACM 2009 |
| 87 |  | Arun Kejariwal,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Utpal Banerjee,
Constantine D. Polychronopoulos:
Efficient Scheduling of Nested Parallel Loops on Multi-Core Systems.
ICPP 2009: 74-83 |
| 86 | | Alexandru Nicolau,
Guangqiang Li,
Alexander V. Veidenbaum,
Arun Kejariwal:
Synchronization optimizations for efficient execution on multi-cores.
ICS 2009: 169-180 |
| 85 | | Maja Etinski,
Julita Corbalán,
Jesús Labarta,
Mateo Valero,
Alexander V. Veidenbaum:
Power-aware load balancing of large scale MPI applications.
IPDPS 2009: 1-8 |
| 84 | | Darshan Desai,
Gerolf Hoflehner,
Arun Kejariwal,
Daniel M. Lavery,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Cameron McNairy:
Performance Characterization of Itanium® 2-Based Montecito Processor.
SPEC Benchmark Workshop 2009: 36-56 |
| 83 | | Arun Kejariwal,
Alexandru Nicolau,
Utpal Banerjee,
Alexander V. Veidenbaum,
Constantine D. Polychronopoulos:
Cache-aware partitioning of multi-dimensional iteration spaces.
SYSTOR 2009: 15 |
| 82 | | Arun Kejariwal,
Alexander V. Veidenbaum,
Alexandru Nicolau,
Milind Girkar,
Xinmin Tian,
Hideki Saito:
On the exploitation of loop-level parallelism in embedded applications.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
| 81 | | Jayram Moorkanikara Nageswaran,
Andrew Felch,
Ashok Chandrasekhar,
Nikil Dutt,
Richard Granger,
Alex Nicolau,
Alexander V. Veidenbaum:
Brain Derived Vision Algorithm on High Performance Architectures.
International Journal of Parallel Programming 37(4): 345-369 (2009) |
| 80 | | Jayram Moorkanikara Nageswaran,
Nikil D. Dutt,
Jeffrey L. Krichmar,
Alex Nicolau,
Alexander V. Veidenbaum:
A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors.
Neural Networks 22(5-6): 791-800 (2009) |
| 2008 |
|---|
| 79 | | Houman Homayoun,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
CASES 2008: 197-206 |
| 78 | | Houman Homayoun,
Sudeep Pasricha,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
DAC 2008: 68-71 |
| 77 | | Houman Homayoun,
Alexander V. Veidenbaum,
Jean-Luc Gaudiot:
Adaptive techniques for leakage power management in L2 cache peripheral circuits.
ICCD 2008: 563-569 |
| 76 | | Houman Homayoun,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
ICCD 2008: 699-706 |
| 75 | | Miquel Pericàs,
Adrián Cristal,
Francisco J. Cazorla,
Rubén González,
Alexander V. Veidenbaum,
Daniel A. Jiménez,
Mateo Valero:
A Two-Level Load/Store Queue Based on Execution Locality.
ISCA 2008: 25-36 |
| 74 | | Carmen Badea,
Alexandru Nicolau,
Alexander V. Veidenbaum:
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems.
LCTES 2008: 23-30 |
| 73 | | Houman Homayoun,
Sudeep Pasricha,
Mohammad A. Makhzan,
Alexander V. Veidenbaum:
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
LCTES 2008: 71-78 |
| 72 | | Isidro Gonzalez,
Marco Galluzzi,
Alexander V. Veidenbaum,
Marco A. Ramírez,
Adrián Cristal,
Mateo Valero:
A distributed processor state management architecture for large-window processors.
MICRO 2008: 11-22 |
| 71 | | Arun Kejariwal,
Alexandru Nicolau,
Utpal Banerjee,
Alexander V. Veidenbaum,
Constantine D. Polychronopoulos:
Cache-aware iteration space partitioning.
PPOPP 2008: 269-270 |
| 70 | | Jelena Trajkovic,
Alexander V. Veidenbaum,
Arun Kejariwal:
Improving SDRAM access energy efficiency for low-power embedded systems.
ACM Trans. Embedded Comput. Syst. 7(3): (2008) |
| 69 | | José Luis Ayala,
Marisa López-Vallejo,
Carlos A. López-Barrio,
Alexander V. Veidenbaum:
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
IJES 3(4): 285-293 (2008) |
| 68 | | Juan L. Aragón,
Alexander V. Veidenbaum:
Optimizing CAM-based instruction cache designs for low-power embedded systems.
Journal of Systems Architecture - Embedded Systems Design 54(12): 1155-1163 (2008) |
| 2007 |
|---|
| 67 | | Carmen Badea,
Alexandru Nicolau,
Alexander V. Veidenbaum:
A simplified java bytecode compilation system for resource-constrained embedded processors.
CASES 2007: 218-228 |
| 66 | | Houman Homayoun,
Alexander V. Veidenbaum:
Reducing leakage power in peripheral circuits of L2 caches.
ICCD 2007: 230-237 |
| 65 | | Jeff Furlong,
Andrew Felch,
Jayram Moorkanikara Nageswaran,
Nikil Dutt,
Alex Nicolau,
Alexander V. Veidenbaum,
Ashok Chandrashekar,
Richard Granger:
Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements.
PARCO 2007: 767-776 |
| 64 | | Arun Kejariwal,
Xinmin Tian,
Milind Girkar,
Wei Li,
Sergey Kozhukhov,
Utpal Banerjee,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Constantine D. Polychronopoulos:
Tight analysis of the performance potential of thread speculation using spec CPU 2006.
PPOPP 2007: 215-225 |
| 63 | | Arun Kejariwal,
Gerolf Hoflehner,
Darshan Desai,
Daniel M. Lavery,
Alexandru Nicolau,
Alexander V. Veidenbaum:
Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture.
SIGMETRICS 2007: 361-362 |
| 62 | | Weiyu Tang,
Arun Kejariwal,
Alexander V. Veidenbaum,
Alexandru Nicolau:
A predictive decode filter cache for reducing power consumption in embedded processors.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 2006 |
|---|
| 61 | | Arun Kejariwal,
Alexander V. Veidenbaum,
Alexandru Nicolau,
Milind Girkar,
Xinmin Tian,
Hideki Saito:
Challenges in exploitation of loop parallelism in embedded applications.
CODES+ISSS 2006: 173-180 |
| 60 | | Milind Girkar,
Arun Kejariwal,
Xinmin Tian,
Hideki Saito,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Constantine D. Polychronopoulos:
Probablistic Self-Scheduling.
Euro-Par 2006: 253-264 |
| 59 | | Dan Nicolaescu,
Babak Salamat,
Alexander V. Veidenbaum:
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.
ICCD 2006 |
| 58 | | Arun Kejariwal,
Xinmin Tian,
Wei Li,
Milind Girkar,
Sergey Kozhukhov,
Hideki Saito,
Utpal Banerjee,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Constantine D. Polychronopoulos:
On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings.
ICS 2006: 24 |
| 2005 |
|---|
| 57 | | Juan L. Aragón,
Alexander V. Veidenbaum:
Energy-Effective Instruction Fetch Unit for Wide Issue Processors.
Asia-Pacific Computer Systems Architecture Conference 2005: 15-27 |
| 56 | | Ana Azevedo,
Arun Kejariwal,
Alexander V. Veidenbaum,
Alexandru Nicolau:
High performance annotation-aware JVM for Java cards.
EMSOFT 2005: 52-61 |
| 55 | | Marco A. Ramírez,
Adrián Cristal,
Mateo Valero,
Alexander V. Veidenbaum,
Luis Villa:
A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.
ICCD 2005: 647-653 |
| 54 | | Rubén González,
Adrián Cristal,
Miquel Pericàs,
Mateo Valero,
Alexander V. Veidenbaum:
An asymmetric clustered processor based on value content.
ICS 2005: 61-70 |
| 53 | | Paolo D'Alberto,
Alexandru Nicolau,
Alexander V. Veidenbaum,
Rajesh K. Gupta:
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.
IEEE Trans. Computers 54(2): 185-197 (2005) |
| 2004 |
|---|
| 52 | | Juan L. Aragón,
Dan Nicolaescu,
Alexander V. Veidenbaum,
Ana-Maria Badulescu:
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors.
DATE 2004: 1374-1375 |
| 51 | | Alexander V. Veidenbaum,
Dan Nicolaescu:
Low Energy, Highly-Associative Cache Design for Embedded Processors.
ICCD 2004: 332-335 |
| 50 | | Rubén González,
Adrián Cristal,
Daniel Ortega,
Alexander V. Veidenbaum,
Mateo Valero:
A Content Aware Integer Register File Organization.
ISCA 2004: 314-324 |
| 49 | | Dan Nicolaescu,
Alexander V. Veidenbaum,
Alexandru Nicolau:
Caching Values in the Load Store Queue.
MASCOTS 2004: 580-587 |
| 48 | | Miquel Pericàs,
Rubén González,
Adrián Cristal,
Alexander V. Veidenbaum,
Mateo Valero:
An Optimized Front-End Physical Register File with Banking and Writeback Filtering.
PACS 2004: 1-14 |
| 47 | | Alexander V. Veidenbaum:
Guest Editor's Introduction: Application-Specific Processors.
IEEE Micro 24(3): 8-9 (2004) |
| 46 | | Marco A. Ramírez,
Adrián Cristal,
Mateo Valero,
Alexander V. Veidenbaum,
Luis Villa:
A partitioned instruction queue to reduce instruction wakeup energy.
IJHPCN 1(4): 153-161 (2004) |
| 2003 |
|---|
| 45 | | Alexander V. Veidenbaum,
Kazuki Joe,
Hideharu Amano,
Hideo Aiso:
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings
Springer 2003 |
| 44 | | José L. Ayala,
Marisa Luisa López-Vallejo,
Alexander V. Veidenbaum,
Carlos A. Lopez:
Energy Aware Register File Implementation through Instruction Predecode.
ASAP 2003: 86-96 |
| 43 | | Dan Nicolaescu,
Alexander V. Veidenbaum,
Alexandru Nicolau:
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.
DATE 2003: 11064-11069 |
| 42 | | Sudeep Pasricha,
Alexander V. Veidenbaum:
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches.
ICCD 2003: 526-531 |
| 41 | | Marco A. Ramírez,
Adrián Cristal,
Alexander V. Veidenbaum,
Luis Villa,
Mateo Valero:
A Simple Low-Energy Instruction Wakeup Mechanism.
ISHPC 2003: 99-112 |
| 40 | | Dan Nicolaescu,
Alexander V. Veidenbaum,
Alexandru Nicolau:
Reducing data cache energy consumption via cached load/store queue.
ISLPED 2003: 252-257 |
| 39 | | Paolo D'Alberto,
Alexandru Nicolau,
Alexander V. Veidenbaum:
A Data Cache with Dynamic Mapping.
LCPC 2003: 436-450 |
| 38 | | Alex Orailoglu,
Alexander V. Veidenbaum:
Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Design & Test of Computers 20(1): 6-7 (2003) |
| 37 | | José L. Ayala,
Alexander V. Veidenbaum,
Marisa Luisa López-Vallejo:
Power-Aware Compilation for Register File Energy Reduction.
International Journal of Parallel Programming 31(6): 451-467 (2003) |
| 2002 |
|---|
| 36 | | Ana Azevedo,
Ilya Issenin,
Radu Cornea,
Rajesh Gupta,
Nikil D. Dutt,
Alexander V. Veidenbaum,
Alexandru Nicolau:
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints.
DATE 2002: 168-175 |
| 35 | | Weiyu Tang,
Alexander V. Veidenbaum,
Alexandru Nicolau,
Rajesh K. Gupta:
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.
ISHPC 2002: 120-132 |
| 34 | | Alexander V. Veidenbaum:
Guest Editor's Introduction.
International Journal of Parallel Programming 30(4): 223-224 (2002) |
| 2001 |
|---|
| 33 | | Alexander V. Veidenbaum:
Guest Editor's Introduction.
International Journal of Parallel Programming 29(5): 461-462 (2001) |
| 2000 |
|---|
| 32 | | Xiaomei Ji,
Dan Nicolaescu,
Alexander V. Veidenbaum,
Alexandru Nicolau,
Rajesh K. Gupta:
Compiler-Directed Cache Assist Adaptivity.
ISHPC 2000: 88-104 |
| 31 | | Dan Nicolaescu,
Xiaomei Ji,
Alexander V. Veidenbaum,
Alexandru Nicolau,
Rajesh K. Gupta:
Compiler-Directed Cache Line Size Adaptivity.
Intelligent Memory Systems 2000: 183-187 |
| 30 | | Sunil Kim,
Alexander V. Veidenbaum:
On Interaction between Interconnection Network Design and Latency Hiding Techniques in Multiprocessors.
The Journal of Supercomputing 16(3): 197-216 (2000) |
| 1999 |
|---|
| 29 | | Alexander V. Veidenbaum,
Weiyu Tang,
Rajesh K. Gupta,
Alexandru Nicolau,
Xiaomei Ji:
Adapting cache line size to application behavior.
International Conference on Supercomputing 1999: 145-154 |
| 28 | | Alexander V. Veidenbaum,
Qingbo Zhao,
Abduhl Shameer:
Non-Sequential Instruction Cache Prefetching for Multiple-issue Processors.
International Journal of High Speed Computing 10(1): 115-140 (1999) |
| 27 | | Edward H. Gornish,
Alexander V. Veidenbaum:
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors.
International Journal of Parallel Programming 27(1): 35-70 (1999) |
| 26 | | Sunil Kim,
Alexander V. Veidenbaum:
Interconnection network organization and its impact on performance and cost in shared memory multiprocessors.
Parallel Computing 25(3): 283-309 (1999) |
| 1998 |
|---|
| 25 | | Alexander V. Veidenbaum,
Pen-Chung Yew,
David J. Kuck,
Constantine D. Polychronopoulos,
David A. Padua,
Edward S. Davidson,
Kyle Gallivan:
Retrospective: The Cedar System.
25 Years ISCA: Retrospectives and Reprints 1998: 89-91 |
| 1997 |
|---|
| 24 | | Sunil Kim,
Alexander V. Veidenbaum:
Stride-directed Prefetching for Secondary Caches.
ICPP 1997: 314- |
| 23 | | Sunil Kim,
Alexander V. Veidenbaum:
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems.
IEEE PACT 1997: 40-51 |
| 22 | | Alexander V. Veidenbaum:
Instruction Cache Prefetching Using Multilevel Branch Prediction.
ISHPC 1997: 51-70 |
| 1995 |
|---|
| 21 | | Sunil Kim,
Alexander V. Veidenbaum:
On Shortest Path Routing in Single Stage Shuffle-Exchange Networks.
SPAA 1995: 298-307 |
| 1994 |
|---|
| 20 | | Edward H. Gornish,
Alexander V. Veidenbaum:
An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors.
ICPP 1994: 281-284 |
| 19 | | Stephen W. Turner,
Alexander V. Veidenbaum:
Scalability of the Cedar system.
SC 1994: 247-254 |
| 1993 |
|---|
| 18 | | Yung-Chin Chen,
Alexander V. Veidenbaum:
Performance Evaluation of Memory Caches in Multiprocessors.
ICPP 1993: 184-187 |
| 17 | | David J. Kuck,
Edward S. Davidson,
Duncan H. Lawrie,
Ahmed H. Sameh,
Chuan-Qi Zhu,
Alexander V. Veidenbaum,
Jeff Konicek,
Pen-Chung Yew,
Kyle Gallivan,
William Jalby,
Harry A. G. Wijshoff,
Randall Bramley,
U. M. Yang,
Perry A. Emrath,
David A. Padua,
Rudolf Eigenmann,
Jay Hoeflinger,
Greg Jaxon,
Zhiyuan Li,
T. Murphy,
John T. Andrews,
Stephen W. Turner:
The Cedar System and an Initial Performance Study.
ISCA 1993: 213-223 |
| 1992 |
|---|
| 16 | | Yung-Chin Chen,
Alexander V. Veidenbaum:
An Effective Write Policy for Software Coherence Schemes.
SC 1992: 661-672 |
| 1991 |
|---|
| 15 | | Jeff Konicek,
Tracy Tilton,
Alexander V. Veidenbaum,
Chuan-Qi Zhu,
Edward S. Davidson,
Ruppert A. Downing,
Michael J. Haney,
Manish Sharma,
Pen-Chung Yew,
P. Michael Farmwald,
David J. Kuck,
Daniel M. Lavery,
Robert A. Lindsey,
D. Pointer,
John T. Andrews,
Thomas Beck,
T. Murphy,
Stephen W. Turner,
Nancy J. Warter:
The Organization of the Cedar System.
ICPP (1) 1991: 49-56 |
| 14 | | Kyle Gallivan,
William Jalby,
Stephen W. Turner,
Alexander V. Veidenbaum,
Harry A. G. Wijshoff:
Preliminary Performance Analysis of the Cedar Multiprocessor Memory System.
ICPP (1) 1991: 71-75 |
| 13 | | Elana D. Granston,
Alexander V. Veidenbaum:
An Integrated Hardware/Software Solution for Effective Management of Local Storage in High-Performance Systems.
ICPP (2) 1991: 83-90 |
| 12 | | Yung-Chin Chen,
Alexander V. Veidenbaum:
A software coherence scheme with the assistance of directories.
ICS 1991: 284-294 |
| 11 | | John D. Bruner,
Hoichi Cheong,
Alexander V. Veidenbaum,
Pen-Chung Yew:
Chief: A Parallel Simulation Environment for Parallel Systems.
IPPS 1991: 568-575 |
| 10 | | Yung-Chin Chen,
Alexander V. Veidenbaum:
Comparison and analysis of software and directory coherence schemes.
SC 1991: 818-829 |
| 9 | | Elana D. Granston,
Alexander V. Veidenbaum:
Detecting redundant accesses to array data.
SC 1991: 854-865 |
| 1990 |
|---|
| 8 | | Edward H. Gornish,
Elana D. Granston,
Alexander V. Veidenbaum:
Compiler-directed data prefetching in multiprocessors with memory hierarchies.
ICS 1990: 354-368 |
| 7 | | Hoichi Cheong,
Alexander V. Veidenbaum:
Compiler-Directed Cache Management in Multiprocessors.
IEEE Computer 23(6): 39-47 (1990) |
| 1989 |
|---|
| 6 | | Hoichi Cheong,
Alexander V. Veidenbaum:
A version control approach to Cache coherence.
ICS 1989: 322-330 |
| 1988 |
|---|
| 5 | | Hoichi Cheong,
Alexander V. Veidenbaum:
Stale Data Detection and Coherence Enforcement Using Flow Analysis.
ICPP (1) 1988: 138-145 |
| 4 | | Stephen W. Turner,
Alexander V. Veidenbaum:
Performance of a shared memory system for vector multiprocessors.
ICS 1988: 315-325 |
| 3 | | Hoichi Cheong,
Alexander V. Veidenbaum:
A Cache Coherence Scheme With Fast Selective Invalidation.
ISCA 1988: 299-307 |
| 1987 |
|---|
| 2 | | Hoichi Cheong,
Alexander V. Veidenbaum:
The Performance of Software-managed Multiprocessor Caches on Parallel Numerical Programs.
ICS 1987: 316-337 |
| 1986 |
|---|
| 1 | | Alexander V. Veidenbaum:
A Compiler-Assisted Cache Coherence Solution for Multiprcessors.
ICPP 1986: 1029-1036 |
