Andreas G. Veneris

	2009
53		Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva: Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI 2009: 345-350
52		Andreas G. Veneris, Sean Safarpour: The day Sherlock Holmes decided to do EDA. DAC 2009: 631-634
51		Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Smith: Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703
50		Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris: Automated data analysis solutions to silicon debug. DATE 2009: 982-987
49		Brian Keng, Andreas G. Veneris: Scaling VLSI design debugging with interpolation. FMCAD 2009: 144-151
	2008
48		Brian Keng, Hratch Mangassarian, Andreas G. Veneris: A succinct memory model for automated design debugging. ICCAD 2008: 137-142
47		Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris: On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS 2008: 123-128
46		Elham Safi, Andreas Moshovos, Andreas G. Veneris: A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED 2008: 233-236
45		Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. VLSI Syst. 16(6): 628-638 (2008)
	2007
44		Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton: Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407
43		Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian: Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937
42		Sean Safarpour, Andreas G. Veneris: Abstraction and refinement techniques in automated design debugging. DATE 2007: 1182-1187
41		Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543
40		Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah: Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19
39		Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Smith: A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245
38		Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni: On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382
	2006
37		Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471
36		Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
35		Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006
34		Elham Safi, Andreas Moshovos, Andreas G. Veneris: L-CBF: a low-power, fast counting bloom filter architecture. ISLPED 2006: 250-255
33		Sean Safarpour, Andreas G. Veneris: Abstraction and Refinement Techniques in Automated Design Debugging. MTV 2006: 88-93
32		Andreas G. Veneris, Yiorgos Makris: Session Abstract. VTS 2006: 290-291
31		Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. VLSI Syst. 14(7): 763-776 (2006)
	2005
30		Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour: Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196
29		Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
28		Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE 2005: 996-1001
27		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
26		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
25		Alexander Smith, Andreas G. Veneris, Moayad Fahim Ali, Anastasios Viglas: Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1606-1621 (2005)
24		Jiang Brandon Liu, Andreas G. Veneris: Incremental fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 240-251 (2005)
23		Andreas G. Veneris, Jiang Brandon Liu: Incremental Design Debugging in a Logic Synthesis Environment. J. Electronic Testing 21(5): 485-494 (2005)
22		Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi: Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electronic Testing 21(5): 495-502 (2005)
	2004
21		Alexander Smith, Andreas G. Veneris, Anastasios Viglas: Design diagnosis using Boolean satisfiability. ASP-DAC 2004: 218-223
20		Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee: Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265
19		Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
18		Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri: Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) 2004: 221-224
17		Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
16		Andreas G. Veneris: Logic Rewiring for Delay and Power Minimization. J. Inf. Sci. Eng. 20(6): 1231-1238 (2004)
	2003
15		Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Diagnosis and Correction in High-Performance Designs. ITC 2003: 423-430
14		Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV 2003: 54-59
13		Andreas G. Veneris: Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. MTV 2003: 60-
	2002
12		Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir: Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE 2002: 716-721
11		Mandana Amiri, Andreas G. Veneris, Ivor Ting: Design rewiring for power minimization [logic design]. ISCAS (4) 2002: 305-308
10		Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Takahashi: Incremental Diagnosis of Multiple Open-Interconnects. ITC 2002: 1085-1092
9		Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri: Design Rewiring Using ATPG. ITC 2002: 223-232
8		Andreas G. Veneris, Magdy S. Abadir: Design rewiring using ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1469-1479 (2002)
	2001
7		Andreas G. Veneris, Magdy S. Abadir, Ivor Ting: Design rewiring based on diagnosis techniques. ASP-DAC 2001: 479-484
	1999
6		Andreas G. Veneris, Ibrahim N. Hajj: Correcting multiple design errors in digital VLSI circuits. ISCAS (1) 1999: 31-34
5		Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs: Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS 1999: 58-63
4		Andreas G. Veneris, Ibrahim N. Hajj: Design error diagnosis and correction via test vector simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1803-1816 (1999)
	1997
3		Andreas G. Veneris, Ibrahim N. Hajj: A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. Great Lakes Symposium on VLSI 1997: 45-50
	1995
2		Lefteris M. Kirousis, Andreas G. Veneris: Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations Acta Inf. 32(2): 155-170 (1995)
	1993
1		Lefteris M. Kirousis, Andreas G. Veneris: Efficient Algorithms for Checking the Atomicity of a Run of Read and Write Operations. WDAG 1993: 54-68

Coauthor Index

1	Magdy S. Abadir	[7] [8] [9] [12] [17] [18] [19] [22] [26] [27] [30] [41]
2	Patrick Akl	[38]
3	Moayad Fahim Ali	[17] [19] [25] [26] [27]
4	Sobeeh Almukhaizim	[47]
5	Mandana Amiri	[9] [11] [12] [18]
6	Angela Arapoyanni (Aggeliki Arapoyanni)	[38]
7	Gregg Baeckler	[37]
8	Marco Benedetti	[39]
9	Robert K. Brayton	[44] [51]
10	Robert Chang	[18] [22]
11	Yibin Chen	[53]
12	Rolf Drechsler	[17] [19] [20] [26] [27] [29] [35] [36]
13	Görschwin Fey	[29] [36]
14	W. Kent Fuchs	[5]
15	Ibrahim N. Hajj	[3] [4] [5] [6]
16	Brian Keng	[48] [49]
17	Lefteris M. Kirousis	[1] [2]
18	Joanne Lee	[20]
19	Mark H. Liffiton	[40]
20	Jiang Brandon Liu	[10] [12] [14] [15] [23] [24] [30]
21	Yiorgos Makris	[32] [47]
22	Hratch Mangassarian	[39] [40] [41] [43] [48]
23	Andreas Moshovos	[34] [38] [45] [46]
24	Farid N. Najm	[41]
25	Nicola Nicolici	[50]
26	Sean Safarpour	[17] [19] [20] [26] [27] [29] [30] [33] [35] [36] [37] [39] [40] [41] [42] [43] [52] [53]
27	Elham Safi	[34] [38] [45] [46]
28	Karem A. Sakallah	[40]
29	Freescale Semiconductor	[17]
30	Sep Seyedi	[22]
31	João P. Marques Silva (João Marques-Silva)	[53]
32	Subarna Sinha	[51]
33	Subarnarekha Sinha	[44]
34	Alexander Smith	[17] [19] [21] [25]
35	Duncan Smith	[39] [51]
36	Hiroshi Takahashi	[10]
37	Paul J. Thadikaran	[14] [15] [28] [31]
38	Ivor Ting	[7] [11]
39	Srikanth Venkataraman	[5] [28] [31]
40	Anastasios Viglas	[21] [25]
41	Yu-Shen Yang	[14] [15] [28] [31] [44] [47] [50] [51]
42	Richard Yuan	[37]

Colors in the list of coauthors