Vyas Venkataraman

	2009
3		Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra: Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344
	2008
2		Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin: Power Balanced Gates Insensitive to Routing Capacitance Mismatch. DATE 2008: 1280-1285
1		Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin, Mark G. Karpovsky: Asynchronous balanced gates tolerant to interconnect variability. ISCAS 2008: 3190-3193

Coauthor Index

1	Jayanta Bhadra	[3]
2	Mrinal Bose	[3]
3	Mark G. Karpovsky	[1]
4	Konrad J. Kulikowski	[1] [2]
5	Wei Qin	[3]
6	Alexander Taubin	[1] [2]
7	Di Wang	[3]
8	Hangsheng Wang	[3]
9	Zhen Wang	[1] [2] [3]