 | 2009 |
|---|
| 10 |       | R. Venkatraman,
R. Castagnetti,
Andres Teene,
Benjamin Mbouombouo,
S. Ramesh:
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.
ISQED 2009: 27-32 |
| 9 | | Parimala Viswanath,
Pranav Murthy,
Debajit Das,
R. Venkatraman,
Ajoy Mandal,
Arvind Veeravalli,
H. Udayakumar:
Optimization strategies to improve statistical timing.
ISQED 2009: 476-481 |
| 8 | | R. Venkatraman,
Shrikrishna Pundoor,
Arun Koithyar,
Madhusudan Rao,
Jagdish C. Rao:
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions.
VLSI Design 2009: 525-530 |
| 2006 |
|---|
| 7 | | R. Venkatraman,
R. Castagnetti,
S. Ramesh:
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.
ISQED 2006: 190-195 |
| 6 | | Bhaskar J. Karmakar,
V. Kalyana Chakravarty,
R. Venkatraman,
Jagdish C. Rao:
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC.
ISQED 2006: 769-774 |
| 2005 |
|---|
| 5 | | R. Castagnetti,
R. Venkatraman,
B. Bartz,
C. Monzel,
T. Briscoe,
Andres Teene,
S. Ramesh:
A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.
ISQED 2005: 193-196 |
| 2003 |
|---|
| 4 | | F. Duan,
R. Castagnetti,
R. Venkatraman,
O. Kobozeva,
S. Ramesh:
Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.
ISQED 2003: 119-124 |
| 2002 |
|---|
| 3 | | Karanth Shankaranarayana,
Soujanna Sarkar,
R. Venkatraman,
Shyam S. Jagini,
N. Venkatesh,
Jagdish C. Rao,
H. Udayakumar,
M. Sambandam,
K. P. Sheshadri,
S. Talapatra,
Parag Mhatre,
Jais Abraham,
Rubin A. Parekhji:
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.
VLSI Design 2002: 781-788 |
| 2000 |
|---|
| 2 | | R. Venkatraman,
Lalit M. Patnaik:
An evolutionary approach to timing driven FPGA placement.
ACM Great Lakes Symposium on VLSI 2000: 81-85 |
| 1 | | R. Venkatraman,
S. Venkatraman:
Rule-based system application for a technical problem in inventory issue.
AI in Engineering 14(2): 143-152 (2000) |
