Haridimos T. Vergos

	2010
32		Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou: Fast modulo 2n+1 multi-operand adders and residue generators. Integration 43(1): 42-48 (2010)
	2009
31		Haridimos T. Vergos, Costas Efstathiou: Efficient modulo 2n+1 adder architectures. Integration 42(2): 149-157 (2009)
	2008
30		Haridimos T. Vergos, Dimitris Bakalis: On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD 2008: 752-759
	2007
29		Haridimos T. Vergos: An Efficient BIST Scheme for Non-Restoring Array Dividers. DSD 2007: 664-667
	2006
28		Haridimos T. Vergos, Costas Efstathiou: Novel Modulo 2n + 1 Multipliers. DSD 2006: 168-175
27		Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos: A core generator for arithmetic cores and testing structures with a network interface. Journal of Systems Architecture 52(1): 1-12 (2006)
	2005
26		Nikolaos Kostaras, Haridimos T. Vergos: KoVer: A Sophisticated Residue Arithmetic Core Generator. IEEE International Workshop on Rapid System Prototyping 2005: 261-263
25		Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos: Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers 54(4): 491-496 (2005)
24		Haridimos T. Vergos, Costas Efstathiou: On the Design of Efficient Modular Adders. Journal of Circuits, Systems, and Computers 14(5): 965-972 (2005)
	2004
23		Haridimos T. Vergos, Costas Efstathiou: Diminished-1 Modulo 2n + 1 Squarer Design. DSD 2004: 380-386
22		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Modified Booth Modulo 2n-1 Multipliers. IEEE Trans. Computers 53(3): 370-374 (2004)
21		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers 53(9): 1211-1216 (2004)
	2003
20		Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP 2003: 326-336
19		D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou: An Efficient BIST scheme for High-Speed Adders. IOLTS 2003: 89-93
18		Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders. ISCAS (5) 2003: 225-228
17		D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou: Efficient BIST schemes for RNS datapaths. ISCAS (5) 2003: 573-576
16		Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos: Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers 52(11): 1399-1406 (2003)
15		Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou: Deterministic BIST for RNS Adders. IEEE Trans. Computers 52(7): 896-906 (2003)
	2002
14		Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos: Diminished-One Modulo 2n+1 Adder Design. IEEE Trans. Computers 51(12): 1389-1399 (2002)
13		Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou: On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. Journal of Systems Architecture 48(4-5): 125-135 (2002)
	2001
12		Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou: High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217
11		Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos: On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED 2001: 350-
	2000
10		Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos: Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED 2000: 433-438
9		Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos: High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers 49(7): 673-680 (2000)
	1999
8		G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos: Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium 1999: 47-52
7		Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas: Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116
6		Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou: Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT 1999: 121-129
5		Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos: Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC 1999: 267-282
4		Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis: On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23
3		C. Ninos, Haridimos T. Vergos, Dimitris Nikolos: Design and Analysis of On-Chip CPU Pipelined Caches. VLSI 1999: 161-172
2		Dimitris Nikolos, Haridimos T. Vergos: On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers 48(10): 1138-1144 (1999)
	1996
1		Dimitris Nikolos, Haridimos T. Vergos: On the Yield of VLSI Processors with on-chip CPU Cache. EDCC 1996: 214-230

Coauthor Index

1	K. Adaos	[27]
2	George Alexiou (G. Ph. Alexiou)	[6] [10] [13] [27]
3	Dimitris Bakalis	[6] [10] [11] [13] [27] [30] [32]
4	Maciej Bellos	[5] [15] [27]
5	Giorgos Dimitrakopoulos	[18] [20] [25]
6	Costas Efstathiou	[9] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [28] [31] [32]
7	Themistoklis Haniotakis (Th. Haniotakis)	[4] [7]
8	John Kalamatianos	[9]
9	Lampros Kalampoukas	[9]
10	Emmanouil Kalligeros	[10] [13]
11	Xrysovalantis Kavousianos	[6] [11]
12	Nikolaos Kostaras	[26]
13	D. Lymperopoulos	[27]
14	Michael Nicolaidis	[4]
15	D. G. Nikolos	[17] [19]
16	Dimitris Nikolos	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [25] [27]
17	C. Ninos	[3]
18	G. Sidiropoulos	[8]
19	Yiorgos Tsiatouhas (Y. Tsiatouhas)	[4] [7]

Colors in the list of coauthors