Juan de Vicente Coauthor index DBLP Vis pubzone.org

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DBLP keys2004
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJuan de Vicente, Juan Lanchares, Román Hermida: Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. 9(3): 310-332 (2004)
2002
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJuan de Vicente, Juan Lanchares, Román Hermida: FPGA Placement by Thermodynamic Combinatorial Optimization. DATE 2002: 54-60
2000
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJuan de Vicente, Juan Lanchares, Román Hermida: Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping 2000: 188-193
1999
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJuan de Vicente, Juan Lanchares, Román Hermida: Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL 1999: 91-100
1998
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJuan de Vicente, Juan Lanchares, Román Hermida: RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO 1998: 10192-10195

Coauthor Index

1Román Hermida [1] [2] [3] [4] [5]
2Juan Lanchares [1] [2] [3] [4] [5]

Copyright © Mon Dec 7 15:48:47 2009 by Michael Ley (ley@uni-trier.de)