Muralidaran Vijayaraghavan Coauthor index DBLP Vis pubzone.org

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DBLP keys2008
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan: High-throughput Pipelined Mergesort. MEMOCODE 2008: 155-158
2007
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMan Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks: From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. MEMOCODE 2007: 71-80
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan: Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. MEMOCODE 2007: 97-100

Coauthor Index

1Michael Adler [4] [5]
2 Arvind [2] [4] [5]
3Nirav Dave [1] [2]
4Joel S. Emer [4] [5]
5Kermin Fleming [1] [3]
6Jamey Hicks [2]
7Asif Khan [3]
8Myron King [1] [3]
9Man Cheuk Ng [2] [3]
10Michael Pellauer [1] [4] [5]
11Gopal Raghavan [2]

Copyright © Fri Nov 27 15:43:12 2009 by Michael Ley (ley@uni-trier.de)