Michael Vinov Coauthor index DBLP Vis pubzone.org

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DBLP keys2007
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShady Copty, Itai Jaeger, Yoav Katz, Michael Vinov: Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation. DAC 2007: 891-895
2006
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz, Michael Vinov, Eitan Marcus, Gil Shurek: Constraint-Based Random Stimuli Generation for Hardware Verification. AAAI 2006
2005
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAllon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy: VLIW: a case study of parallelism verification. DAC 2005: 779-782
2004
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMichael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov: Industrial experience with test generation languages for processor verification. DAC 2004: 36-40
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAllon Adir, Eli Almog, Laurent Fournier, Eitan Marcus, Michal Rimon, Michael Vinov, Avi Ziv: Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification. IEEE Design & Test of Computers 21(2): 84-93 (2004)

Coauthor Index

1Allon Adir [1] [3]
2Eli Almog [1]
3Yaron Arbetman [3]
4Michael L. Behm [2]
5Massimo A. Calligaro [3]
6Andrew Cofler [3]
7Shady Copty [5]
8Bella Dubrov [3]
9Gabriel Duffy [3]
10Laurent Fournier [1]
11Itai Jaeger [4] [5]
12Yoav Katz [4] [5]
13Yossi Lichtenstein [2] [3]
14John M. Ludden [2]
15Eitan Marcus [1] [4]
16Yehuda Naveh [4]
17Michal Rimon [1] [2] [3] [4]
18Gil Shurek [4]
19Avi Ziv [1]

Copyright © Tue Dec 1 12:01:14 2009 by Michael Ley (ley@uni-trier.de)