Jörg E. Vollrath

	2006
11		Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson: DDR2 DRAM Output Timing Optimization. MTDT 2006: 49-54
	2005
10		Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439
	2003
9		Jörg E. Vollrath: Output Timing Measurement Using an Idd Method. MTDT 2003: 43-46
8		Jörg E. Vollrath: Testing and Characterization of SDRAMs. IEEE Design & Test of Computers 20(1): 42-50 (2003)
	2002
7		Jörg E. Vollrath: Signal Margin Analysis for Memory Sense Amplifiers . DELTA 2002: 123-127
	2001
6		Jörg E. Vollrath, Randall Rooney: Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment. ITC 2001: 768-775
5		Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik: Compressed Bit Fail Maps for Memory Fail Pattern Classification. J. Electronic Testing 17(3-4): 291-297 (2001)
	2000
4		Jörg E. Vollrath: Synchronous Dynamic Memory Test Construction: A Field Approach. MTDT 2000: 59-64
	1999
3		Jörg E. Vollrath: Tutorial: Characterizing SDRAMS. MTDT 1999: 62-
	1998
2		Jörg E. Vollrath, Markus Huebl, Ernst Stahl: Power Analysis of DRAMs. Asian Test Symposium 1998: 334-339
	1997
1		Jörg E. Vollrath: Cell Signal Measurement for High-Density DRAMs. ITC 1997: 209-216

Coauthor Index

1	Zaid Al-Ars	[10]
2	Marcin Gnat	[11]
3	Said Hamdioui	[10]
4	Thomas Hladschik	[5]
5	Markus Huebl	[2]
6	Bret Johnson	[11]
7	Ulf Lederer	[5]
8	Randall Rooney	[6]
9	Ralf Schneider	[11]
10	Jürg Schwizer	[11]
11	Ernst Stahl	[2]

Colors in the list of coauthors