Robert A. Walker

other persons with the same name:

• Robert A. Walker

	2008
32		Ken W. Batcher, Robert A. Walker: Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. DATE 2008: 260-263
31		Kevin Schaffer, Robert A. Walker: Using hardware multithreading to overcome broadcast/reduction latency in an associative SIMD processor. IPDPS 2008: 1-7
30		Kevin Schaffer, Robert A. Walker: Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor. Parallel Processing Letters 18(4): 491-509 (2008)
	2007
29		Kevin Schaffer, Robert A. Walker: A Prototype Multithreaded Associative SIMD Processor. IPDPS 2007: 1-6
	2006
28		Ken W. Batcher, Robert A. Walker: Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache. IEEE Real Time Technology and Applications Symposium 2006: 91-102
27		Charles J. Colbourn, Sosina Martirosyan, Tran van Trung, Robert A. Walker: Roux-type constructions for covering arrays of strengths three and four. Des. Codes Cryptography 41(1): 33-57 (2006)
	2005
26		Hong Wang, Robert A. Walker: A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications. IASTED PDCS 2005: 667-673
	2004
25		Kenneth E. Batcher, Robert A. Walker: Cluster miss prediction for instruction caches in embedded networking applications. ACM Great Lakes Symposium on VLSI 2004: 358-363
24		Ken W. Batcher, Robert A. Walker: Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. CASES 2004: 24-34
23		Hong Wang, Lei Xie, Meiduo Wu, Robert A. Walker: A Scalable Associative Processor with Applications in Database and Image Processing. IPDPS 2004
	2003
22		Hong Wang, Robert A. Walker: Implementing a Scalable ASC Processor. IPDPS 2003: 267
	2002
21		Meiduo Wu, Robert A. Walker, Jerry L. Potter: Implementing Associative Search and Responder Resolution. IPDPS 2002
	2001
20		Robert A. Walker, Jerry L. Potter, Yanping Wang, Meiduo Wu: Implementing Associative Processing: Rethinking EarlierArchitectural Decisions. IPDPS 2001: 195
	2000
19		Stephen A. Blythe, Robert A. Walker: Efficient optimal design space characterization methodologies. ACM Trans. Design Autom. Electr. Syst. 5(3): 322-336 (2000)
	1999
18		Stephen A. Blythe, Robert A. Walker: Efficiently Searching the Optimal Design Space. Great Lakes Symposium on VLSI 1999: 192-
17		Samit Chaudhuri, Robert A. Walker: Bounding Algorithms for Design Space Exploration. Great Lakes Symposium on VLSI 1999: 234-235
16		Robert A. Walker: A practical one-semester "VLSI design" course for computer science (and other) majors. SIGCSE 1999: 237-241
	1997
15		Samit Chaudhuri, S. A. Blthye, Robert A. Walker: A solution methodology for exact design space exploration in a three-dimensional design space. IEEE Trans. VLSI Syst. 5(1): 69-81 (1997)
	1996
14		Stephen A. Blythe, Robert A. Walker: Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. ISSS 1996: 8-13
13		Samit Chaudhuri, Robert A. Walker: Computing lower bounds on functional units before scheduling. IEEE Trans. VLSI Syst. 4(2): 273-279 (1996)
	1995
12		Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker: An exact methodology for scheduling in a 3D design space. ISSS 1995: 78-83
11		Robert A. Walker, Samit Chaudhuri: Introduction to the Scheduling Problem. IEEE Design & Test of Computers 12(2): 60-69 (1995)
	1994
10		Samit Chaudhuri, Robert A. Walker: ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. VLSI Design 1994: 17-20
9		Robert A. Walker: Guest Editor's Introduction: The Status of High-Level Synthesis. IEEE Design & Test of Computers 11(4): 42-43 (1994)
8		Samit Chaudhuri, Robert A. Walker, J. E. Mitchell: Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. IEEE Trans. VLSI Syst. 2(4): 456-471 (1994)
	1993
7		Samit Chaudhuri, Robert A. Walker, John Mitchell: The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. ICCD 1993: 25-29
6		Ching-Tang Chang, Kenneth Rose, Robert A. Walker: Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. ICCD 1993: 374-378
	1991
5		Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland: Increasing User Interaction During High-Level Synthesis. MICRO 1991: 133-142
	1989
4		Robert A. Walker, Donald E. Thomas: Behavioral transformation for algorithmic level IC design. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1115-1128 (1989)
	1988
3		Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn: The System Architect's Workbench. DAC 1988: 337-343
	1985
2		Robert A. Walker, Donald E. Thomas: A model of design representation and synthesis. DAC 1985: 453-459
	1983
1		Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker: Automatic Data Path Synthesis. IEEE Computer 16(12): 59-70 (1983)

Coauthor Index

1	Ken W. Batcher	[24] [28] [32]
2	Kenneth E. Batcher	[25]
3	Robert L. Blackburn	[3]
4	S. A. Blthye	[15]
5	Stephen A. Blythe	[12] [14] [18] [19]
6	Ching-Tang Chang	[6]
7	Samit Chaudhuri	[7] [8] [10] [11] [12] [13] [15] [17]
8	Charles J. Colbourn	[27]
9	Elizabeth M. Dirkes	[3]
10	Steinar Flatland	[5]
11	Charles Y. Hitchcock III	[1]
12	Rajive Joshi	[5]
13	Thaddeus J. Kowalski	[1]
14	Sosina Martirosyan	[27]
15	J. E. Mitchell	[8]
16	John Mitchell	[7]
17	John A. Nestor	[3]
18	Jerry L. Potter	[20] [21]
19	Jayanth V. Rajan	[1] [3]
20	Shivkumar Ramabadran	[5]
21	Kenneth Rose	[6]
22	Kevin Schaffer	[29] [30] [31]
23	Donald E. Thomas	[1] [2] [3] [4]
24	Tran van Trung	[27]
25	Yanping Wang	[20]
26	Hong Wang	[22] [23] [26]
27	Meiduo Wu	[20] [21] [23]
28	Lei Xie	[23]

Colors in the list of coauthors