Albert Wang Coauthor index DBLP Vis pubzone.org

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20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlbert Wang, Earl Killian, Dror E. Maydan, Chris Rowen: Hardware/Software Instruction Set Configurability for System-on-Chip Processors. DAC 2001: 184-188
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJagesh V. Sanghavi, Albert Wang: Estimation of Speed, Area, and Power of Parameterizable, Soft IP. DAC 2001: 31-34
18no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYing Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan: Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. ICCD 2001: 447-452
17no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGavin Minami, Zixiang Xiong, Albert Wang, Sanjeev Mehrotra: 3-D wavelet coding of video with arbitrary regions of support. IEEE Trans. Circuits Syst. Video Techn. 11(9): 1063-1068 (2001)
16no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPhilip A. Chou, Alexander E. Mohr, Albert Wang, Sanjeev Mehrotra: Error control for receiver-driven layered multicast of audio and video. IEEE Transactions on Multimedia 3(1): 108-122 (2001)
2000
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPhilip A. Chou, Alexander E. Mohr, Albert Wang, Sanjeev Mehrotra: FEC and Pseudo-ARQ for Receiver-Driven Layered Multicast of Audio and Video. Data Compression Conference 2000: 440-449
1999
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlbert Wang, Zixiang Xiong, Philip A. Chou, Sanjeev Mehrotra: Three-Dimensional Wavelet Coding of Video with Global Motion Compensation. Data Compression Conference 1999: 404-413
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPhilip A. Chou, Sanjeev Mehrotra, Albert Wang: Multiple Description Decoding of Overcomplete Expansions Using Projections onto Convex Sets. Data Compression Conference 1999: 72-81
1996
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. ACM Trans. Program. Lang. Syst. 18(3): 235-253 (1996)
11no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMaher Kaddoura, Sanjay Ranka, Albert Wang: Array Decompositions for Nonuniform Computational Environments. J. Parallel Distrib. Comput. 36(2): 91-105 (1996)
1995
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Code Optimization Techniques for Embedded DSP Microprocessors. DAC 1995: 599-604
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPeter Vanbekbergen, Albert Wang, Kurt Keutzer: A Design and Validation System for Asynchronous Circuits. DAC 1995: 725-730
8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLStan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert Wang: Storage Assignment to Decrease Code Size. PLDI 1995: 186-195
1994
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGuido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert Wang: Challenges in code generation for embedded processors. Code Generation for Embedded Processors 1994: 48-64
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified timing verification and the transition delay of a logic circuit. IEEE Trans. VLSI Syst. 2(3): 333-342 (1994)
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 814-822 (1994)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. VLSI Signal Processing 7(1-2): 161-182 (1994)
1993
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1924-1936 (1993)
1992
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Certified Timing Verification and the Transition Delay of a Logic Circuit. DAC 1992: 549-555
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang: Verification of asynchronous interface circuits with bounded wire delays. ICCAD 1992: 188-195

Coauthor Index

1Guido Araujo [7]
2Philip A. Chou [13] [14] [15] [16]
3Srinivas Devadas [1] [2] [3] [4] [5] [6] [7] [8] [10] [12]
4Maher Kaddoura [11]
5Kurt Keutzer [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12]
6Earl Killian [20]
7Stan Y. Liao [7] [8] [10] [12]
8Conor F. Madigan [18]
9Sharad Malik [1] [2] [3] [4] [5] [6] [7] [18]
10Dror E. Maydan [20]
11Sanjeev Mehrotra [13] [14] [15] [16] [17]
12Gavin Minami [17]
13Alexander E. Mohr [15] [16]
14Matthew W. Moskewicz [18]
15Sanjay Ranka [11]
16Chris Rowen (Christopher Rowen) [20]
17Jagesh V. Sanghavi [19]
18Ashok Sudarsanam [7]
19Steven W. K. Tjiang [7] [8] [10] [12]
20Peter Vanbekbergen [9]
21Zixiang Xiong [14] [17]
22Ying Zhao [18]

Colors in the list of coauthors

Copyright © Fri Nov 27 15:43:12 2009 by Michael Ley (ley@uni-trier.de)