Chun-Yao Wang

	2009
28		Yung-Chih Chen, Chun-Yao Wang: Enhancing SAT-based sequential depth computation by pruning search space. ACM Great Lakes Symposium on VLSI 2009: 397-400
27		Chen-Hsuan Lin, Chun-Yao Wang: Dependent latch identification in the reachable state space. ASP-DAC 2009: 630-635
26		Chun-Chi Lin, Chun-Yao Wang: Rewiring using IRredundancy Removal and Addition. DATE 2009: 324-327
25		Meng-Syue Chan, Chun-Yao Wang, Yung-Chih Chen: An efficient approach to sip design integration. ISQED 2009: 241-247
24		Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsin Chang: A novel ACO-based pattern generation for peak power estimation in VLSI circuits. ISQED 2009: 317-323
	2008
23		Chun-Yao Wang, Daniel J. Buehrer: A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol. IAT 2008: 395-398
22		Chuang-Chi Chiou, Chun-Yao Wang, Yung-Chih Chen: A Statistic-Based Approach to Testability Analysis. ISQED 2008: 267-270
21		Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou: Verification of Pin-Accurate Port Connections. IEEE Design & Test of Computers 25(5): 478-486 (2008)
20		Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen: Novel Probabilistic Combinational Equivalence Checking. IEEE Trans. VLSI Syst. 16(4): 365-375 (2008)
19		Yung-Chih Chen, Chun-Yao Wang: An Implicit Approach to Minimizing Range-Equivalent Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1942-1955 (2008)
18		Min-Lun Chuang, Chun-Yao Wang: Synthesis of reversible sequential elements. JETC 3(4): (2008)
	2007
17		Min-Lun Chuang, Chun-Yao Wang: Synthesis of Reversible Sequential Elements. ASP-DAC 2007: 420-425
16		Tsung-Lin Lee, Chun-Yao Wang: Recognition of Fanout-free Functions. ASP-DAC 2007: 426-431
15		Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho: Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED 2007: 344-349
14		Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang: A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2222-2227 (2007)
	2006
13		Ming-Hong Su, Chun-Yao Wang: High level equivalence symmetric input identification. ASP-DAC 2006: 249-253
12		Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen: Language-Based High Level Transaction Extraction on On-chip Buses. ISQED 2006: 231-236
11		Shih-Chieh Wu, Chun-Yao Wang: PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking. VLSI-SoC 2006: 104-109
	2005
10		Yung-Chih Chen, Chun-Yao Wang: An Improved Approach for AlternativeWires Identi.cation. ICCD 2005: 711-716
	2004
9		Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou: Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD 2004: 417-419
8		Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang: Verification on Port Connections. ITC 2004: 830-836
7		Daniel J. Buehrer, Chun-Yao Wang: Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans. Web Intelligence 2004: 752-754
	2003
6		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747
5		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003)
	2002
4		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002)
3		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002)
	2001
2		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436
1		Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou: An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262

Coauthor Index

1	Daniel J. Buehrer	[7] [23]
2	Meng-Syue Chan	[25]
3	Shih-Chieh Chang	[12] [15]
4	Ya-Hsin Chang	[24]
5	Po-Yuan Chen	[14]
6	Yung-Chih Chen	[10] [12] [19] [20] [22] [24] [25] [28]
7	Chuang-Chi Chiou	[22]
8	Chen-Ling Chou	[9]
9	Min-Lun Chuang	[17] [18]
10	Pei-Hsin Ho	[15]
11	Wen-Wen Hsieh	[14]
12	Juinn-Dar Huang	[8] [21]
13	Yi-Le Huang	[12]
14	TingTing Hwang	[14]
15	Jing-Yang Jou	[1] [2] [3] [4] [5] [6] [8] [9] [21]
16	Yu-Min Kuo	[15]
17	Geeng-Wei Lee	[8] [9] [21]
18	Tsung-Lin Lee	[16]
19	Chen-Hsuan Lin	[27]
20	Cheng-Hung Lin	[15]
21	Chun-Chi Lin	[26]
22	Yi-Ling Liu	[24]
23	Ming-Hong Su	[13]
24	Shing-Wu Tung	[1] [2] [3] [4] [5] [6]
25	Shih-Chieh Wu	[11] [20]
26	Richard Yeh	[12]

Colors in the list of coauthors