 | 2009 |
|---|
| 8 |       | Renshen Wang,
Chung-Kuan Cheng:
Octilinear redistributive routing in bump arrays.
ACM Great Lakes Symposium on VLSI 2009: 191-196 |
| 7 | | Renshen Wang,
Chung-Kuan Cheng:
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
ACM Great Lakes Symposium on VLSI 2009: 257-262 |
| 6 | | Wanping Zhang,
Yi Zhu,
Wenjian Yu,
Amirali Shayan Arani,
Renshen Wang,
Zhi Zhu,
Chung-Kuan Cheng:
Noise minimization during power-up stage for a multi-domain power network.
ASP-DAC 2009: 391-396 |
| 5 | | Renshen Wang,
Nan-Chi Chou,
Bill Salefski,
Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
DAC 2009: 166-171 |
| 2008 |
|---|
| 4 | | Ling Zhang,
Wenjian Yu,
Yulei Zhang,
Renshen Wang,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
James F. Buckwalter,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects 2008: 51-56 |
| 3 | | Renshen Wang,
Evangeline F. Y. Young,
Yi Zhu,
Fan Chung Graham,
Ronald L. Graham,
Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences.
ISPD 2008: 54-59 |
| 2006 |
|---|
| 2 | | Renshen Wang,
Rui Shi,
Chung-Kuan Cheng:
Layer minimization of escape routing in area array packaging.
ICCAD 2006: 815-819 |
| 2005 |
|---|
| 1 | | Renshen Wang,
Sheqin Dong,
Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List.
ASP-DAC 2005: 1115-1118 |
