Zeyi Wang

	2008
25		Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan: Efficient techniques for 3-D impedance extraction using mixed boundary element method. ASP-DAC 2008: 158-163
24		Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong: An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation. DATE 2008: 580-585
23		Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang: Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1508-1513 (2008)
	2007
22		Xiren Wang, Wenjian Yu, Zeyi Wang: A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates. ASP-DAC 2007: 62-67
	2006
21		Mengsheng Zhang, Wenjian Yu, Yu Du, Zeyi Wang: An efficient algorithm for 3-D reluctance extraction considering high frequency effect. ASP-DAC 2006: 521-526
20		Xiren Wang, Wenjian Yu, Zeyi Wang: A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles. ASP-DAC 2006: 683-688
19		Changhao Yan, Wenjian Yu, Zeyi Wang: Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method. ASP-DAC 2006: 844-849
18		Changhao Yan, Wenjian Yu, Zeyi Wang: A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. ISQED 2006: 709-716
17		Wenjian Yu, Mengsheng Zhang, Zeyi Wang: Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 12-18 (2006)
16		Xiren Wang, Wenjian Yu, Zeyi Wang: Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3035-3042 (2006)
	2005
15		Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong: An improved direct boundary element method for substrate coupling resistance extraction. ACM Great Lakes Symposium on VLSI 2005: 84-87
14		Xiren Wang, Wenjian Yu, Zeyi Wang: Substrate resistance extraction with direct boundary element method. ASP-DAC 2005: 208-211
13		Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang: Improved Boundary Element Method for Fast 3-D Interconnect Resistance Extraction. IEICE Transactions 88-C(2): 232-240 (2005)
	2004
12		Liu Yang, Xiaobo Guo, Zeyi Wang: An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction. ASP-DAC 2004: 702-706
11		Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang: Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method. ASP-DAC 2004: 707-709
10		Zhaozhi Yang, Zeyi Wang: New Multipole Method for 3-D Capacitance Extraction. J. Comput. Sci. Technol. 19(4): 544- (2004)
	2003
9		Wenjian Yu, Zeyi Wang, Xianlong Hong: Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. ICCD 2003: 58-63
	2002
8		Shuzhou Fang, Zeyi Wang, Xianlong Hong: A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. VLSI Design 2002: 305-310
	2001
7		Zhaozhi Yang, Zeyi Wang, Shuzhou Fang: A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. ASP-DAC 2001: 214-218
6		Wenjian Yu, Zeyi Wang: An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects. ASP-DAC 2001: 366-372
	2000
5		Jiangchun Gu, Zeyi Wang, Xianlong Hong: Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. ASP-DAC 2000: 447-452
4		Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong: A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. ASP-DAC 2000: 453-456
	1999
3		Jinsong Hou, Zeyi Wang, Xianlong Hong: The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. ASP-DAC 1999: 93-
	1996
2		Zeyi Wang, Yanhong Yuan, Qiming Wu: A parallel multipole accelerated 3-D capacitance simulator based on an improved model. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1441-1450 (1996)
	1992
1		Zeyi Wang, Qiming Wu: A two-dimensional resistance simulator using the boundary element method. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 497-504 (1992)

Coauthor Index

1	Yu Du	[21]
2	Shuzhou Fang	[4] [7] [8]
3	Fang Gong	[25]
4	Jiangchun Gu	[5]
5	Xiaobo Guo	[12]
6	Xianlong Hong	[3] [4] [5] [8] [9] [15]
7	Jinsong Hou	[3]
8	Rong Jiang	[24]
9	Deyan Liu	[11] [13]
10	Xiaobo Tang	[4]
11	Xiren Wang	[11] [13] [14] [15] [16] [20] [22] [23]
12	Qiming Wu	[1] [2]
13	Jinjun Xiong	[24]
14	Changhao Yan	[18] [19] [25]
15	Liu Yang	[12]
16	Zhaozhi Yang	[7] [10]
17	Zuochang Ye	[23]
18	Wenjian Yu	[6] [9] [11] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
19	Zhiping Yu	[24] [25]
20	Yanhong Yuan	[2]
21	Mengsheng Zhang	[17] [21]
22	Wangyang Zhang	[24]

Colors in the list of coauthors