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| 3 | Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad Kwasniewski: A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE 2009: 1208-1212 | |
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| 2 | Qingsheng Hu, Zhigong Wang, Jun Zhang, Jie Xiao: Low complexity parallel Chien search architecture for RS decoder. ISCAS (1) 2005: 340-343 | |
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| 1 | Zhigong Wang, Ulrich Langmann, Berthold G. Bosch: Multi-Gb/s Silicon Bipolar Clock Recovery IC. IEEE Journal on Selected Areas in Communications 9(5): 656-663 (1991) | |
| 1 | Berthold G. Bosch | [1] |
| 2 | Dianyong Chen | [3] |
| 3 | Qingsheng Hu | [2] |
| 4 | Tad Kwasniewski | [3] |
| 5 | Ulrich Langmann | [1] |
| 6 | Bangli Liang | [3] |
| 7 | Guohui Situ | [3] |
| 8 | Bo Wang | [3] |
| 9 | Jie Xiao | [2] |
| 10 | Jun Zhang | [2] |