Zhongfeng Wang

	2009
32		Kai Zhang, Xinming Huang, Zhongfeng Wang: An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems. ASAP 2009: 235-238
31		Kai Zhang, Xinming Huang, Zhongfeng Wang: High-throughput layered decoder implementation for quasi-cyclic LDPC codes. IEEE Journal on Selected Areas in Communications 27(6): 985-994 (2009)
	2008
30		Zhiqiang Cui, Zhongfeng Wang: Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462
29		Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang: Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. ICCD 2008: 526-531
28		Jinjin He, Jian Cui, Lianxing Yang, Zhongfeng Wang: A low-complexity high-performance noncoherent receiver for GFSK signals. ISCAS 2008: 1256-1259
27		Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang: Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. ISCAS 2008: 3078-3081
26		Jinjin He, Zhongfeng Wang, Huaping Liu: Low-complexity high-speed 4-D TCM decoder. SiPS 2008: 216-220
25		Bainan Chen, Xinmiao Zhang, Zhongfeng Wang: Error correction for multi-level NAND flash memory using Reed-Solomon codes. SiPS 2008: 94-99
	2007
24		Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen: Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 1409-1412
23		Qinqin Chen, Zhongfeng Wang, Jun Ma: FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 2100-2103
22		Zhiqiang Cui, Zhongfeng Wang: Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920
21		Lupin Chen, Jinjin He, Zhongfeng Wang: Design of Low-Power Memory-Efficient Viterbi Decoder. SiPS 2007: 132-135
20		Zhiqiang Cui, Zhongfeng Wang: Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS 2007: 216-221
19		Qingwei Li, Zhongfeng Wang: Early-Pruning K-Best Sphere Decoder for MIMO Systems. SiPS 2007: 40-44
18		Somya Rathi, Zhongfeng Wang: Fast EBCOT Encoder Architecture for JPEG 2000. SiPS 2007: 595-599
17		Zhongfeng Wang, Zhiqiang Cui: Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(1): 104-114 (2007)
16		Jun Ma, Alexander Vardy, Zhongfeng Wang: Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. VLSI Syst. 15(11): 1225-1238 (2007)
15		Zhongfeng Wang, Zhiqiang Cui: A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(4): 483-488 (2007)
	2006
14		Jin Sha, Ming-Lun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang: An FPGA Implementation of Array LDPC Decoder. APCCAS 2006: 1675-1678
13		Zhiqiang Cui, Zhongfeng Wang: A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006
12		Zhiqiang Cui, Zhongfeng Wang: Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006
11		Jun Ma, Alexander Vardy, Zhongfeng Wang: Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes. ISCAS 2006
10		Qingwei Li, Zhongfeng Wang: Improved k-best sphere decoding algorithms for MIMO systems. ISCAS 2006
9		Jun Ma, Alexander Vardy, Zhongfeng Wang: Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code. ISCAS 2006
8		Zhongfeng Wang, Jun Ma: High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. VLSI Syst. 14(9): 937-950 (2006)
	2005
7		Zhongfeng Wang, Qing-wei Jia: Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes. ISCAS (6) 2005: 5786-5789
	2004
6		Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi: On the better protection of short-frame turbo codes. IEEE Transactions on Communications 52(9): 1435-1439 (2004)
	2003
5		Zhongfeng Wang, Yiyan Tang, Yuke Wang: Low hardware complexity parallel turbo decoder architecture. ISCAS (2) 2003: 53-56
	2002
4		Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi: Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. VLSI Syst. 10(6): 902-912 (2002)
	2001
3		Tong Zhang, Zhongfeng Wang, Keshab K. Parhi: On finite precision implementation of low density parity check codes decoder. ISCAS (4) 2001: 202-205
2		Zhongfeng Wang, Hiroshi Suzuki, Keshab K. Parhi: Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders. VLSI Signal Processing 29(3): 209-221 (2001)
	1999
1		S. Summerfield, Zhongfeng Wang, Keshab K. Parhi: Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ISCAS (3) 1999: 343-346

Coauthor Index

1	Bainan Chen	[25]
2	Lupin Chen	[21]
3	Qinqin Chen	[23] [24]
4	Zhipei Chi	[4] [6]
5	Jian Cui	[28]
6	Zhiqiang Cui	[12] [13] [15] [17] [20] [22] [30]
7	Ming-Lun Gao	[14]
8	Jinjin He	[21] [26] [28]
9	Xinming Huang	[31] [32]
10	Qing-wei Jia	[7]
11	Li Li	[14]
12	Qingwei Li	[10] [19]
13	Huaping Liu	[26]
14	Jun Ma	[8] [9] [11] [16] [23] [24]
15	Keshab K. Parhi	[1] [2] [3] [4] [6]
16	Somya Rathi	[18]
17	Jin Sha	[14]
18	S. Summerfield	[1]
19	Hiroshi Suzuki	[2]
20	Yiyan Tang	[5]
21	Alexander Vardy	[9] [11] [16] [24]
22	Yuke Wang	[5]
23	Lianxing Yang	[28]
24	Kai Zhang	[31] [32]
25	Tong Zhang	[3]
26	Xinmiao Zhang	[25] [27] [29]
27	Zhongjin Zhang	[14]
28	Jiangli Zhu	[27] [29]

Colors in the list of coauthors