 | 2009 |
|---|
| 4 |       | Raphael Weber,
Achim Rettberg:
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.
ARC 2009: 330-335 |
| 2007 |
|---|
| 3 |  | Florian Dittmann,
Achim Rettberg,
Raphael Weber:
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture.
ERSA 2007: 152-158 |
| 2 | | Florian Dittmann,
Achim Rettberg,
Raphael Weber:
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture.
SBCCI 2007: 153-158 |
| 2005 |
|---|
| 1 | | Florian Dittmann,
Achim Rettberg,
Raphael Weber:
Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture.
EUC 2005: 448-457 |
