Gu-Yeon Wei

	2009
28		Mark Hempstead, Gu-Yeon Wei, David Brooks: An accelerator-based wireless sensor network processor in 130nm CMOS. CASES 2009: 215-222
27		Vijay Janapa Reddi, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks, Simone Campanoni: Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack. DAC 2009: 788-793
26		Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks: An event-guided approach to reducing voltage noise in processors. DATE 2009: 160-165
25		Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks: Voltage emergency prediction: Using signatures to reduce operating margins. HPCA 2009: 18-29
24		Krishna K. Rangan, Gu-Yeon Wei, David Brooks: Thread motion: fine-grained power management for multi-core systems. ISCA 2009: 302-313
23		Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei: Place and route considerations for voltage interpolated designs. ISQED 2009: 594-600
	2008
22		Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David Brooks: System level analysis of fast, per-core DVFS using on-chip switching regulators. HPCA 2008: 123-134
21		Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David M. Brooks: DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors. HPCA 2008: 381-392
20		Kevin Brownell, Gu-Yeon Wei, David Brooks: Evaluation of voltage interpolation to address process variations. ICCAD 2008: 529-536
19		Michael Karpelson, Gu-Yeon Wei, Robert J. Wood: A review of actuation and power electronics options for flapping-wing robotic insects. ICRA 2008: 779-786
18		Xiaoyao Liang, Gu-Yeon Wei, David Brooks: ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. ISCA 2008: 191-202
17		Mark Hempstead, Gu-Yeon Wei, David Brooks: System design considerations for sensor network applications. ISCAS 2008: 2566-2569
16		Xuning Chen, Gu-Yeon Wei, Li-Shiuan Peh: Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies. ISLPED 2008: 277-282
15		Gu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang: Instruction-driven clock scheduling with glitch mitigation. ISLPED 2008: 357-362
14		Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks: Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability. IEEE Micro 28(1): 60-68 (2008)
	2007
13		Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. DATE 2007: 624-629
12		Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. GLOBECOM 2007: 265-270
11		Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei: Serial Sum-Product Architecture for Low-Density Parity-Check Codes. ICCCN 2007: 154-158
10		Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks: Towards a software approach to mitigate voltage emergencies. ISLPED 2007: 123-128
9		Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks: Process Variation Tolerant 3T1D-Based Cache Architectures. MICRO 2007: 15-26
	2006
8		Mark Hempstead, Gu-Yeon Wei, David Brooks: Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. CASES 2006: 368-378
7		Wai-Chi Fang, Sharon Kedar, Susan Owen, Gu-Yeon Wei, David Brooks, Jonathan Lees: System-on-Chip Architecture Design for Intelligent Sensor Networks. IIH-MSP 2006: 579-582
	2005
6		Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal: Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems. HPCA 2005: 120-131
5		Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks: An Ultra Low Power System Architecture for Sensor Network Applications. ISCA 2005: 208-219
	2004
4		Ruwan N. S. Ratnayake, Gu-Yeon Wei, Aleksandar Kavcic: Pipelined parallel architecture for high throughput MAP detectors. ISCAS (2) 2004: 505-508
3		Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon: Jitter in high-speed serial and parallel links. ISCAS (4) 2004: 425-428
2		Yong-Cheol Bae, Gu-Yeon Wei: A mixed PLL/DLL architecture for low jitter clock generation. ISCAS (4) 2004: 788-791
	1996
1		Gu-Yeon Wei, Mark Horowitz: A low power switching power supply for self-clocked systems. ISLPED 1996: 313-317

Coauthor Index

1	Yong-Cheol Bae	[2]
2	David Brooks	[5] [7] [8] [9] [10] [14] [15] [17] [18] [20] [22] [23] [24] [25] [28]
3	David M. Brooks	[13] [21] [26] [27]
4	Kevin Brownell	[20] [23]
5	Simone Campanoni	[27]
6	Ramon Canal	[9] [14]
7	Bryan Casper	[3]
8	Xuning Chen	[6] [16]
9	Wai-Chi Fang	[7]
10	Meeta Sharma Gupta	[10] [13] [21] [22] [25] [26] [27]
11	Pavan Kumar Hanumolu	[3]
12	Erich F. Haratsch	[11] [12]
13	Mark Hempstead	[5] [8] [17] [28]
14	Glenn H. Holloway	[25] [26]
15	Mark Horowitz	[1]
16	Yue-Kai Huang	[6]
17	Russ Joseph	[13]
18	Michael Karpelson	[19]
19	Aleksandar Kavcic	[4]
20	Sharon Kedar	[7]
21	Ali Durlov Khan	[15] [23]
22	Wonyoung Kim	[22]
23	Jonathan Lees	[7]
24	Xiaoyao Liang	[9] [14] [15] [18]
25	Patrick Mauro	[5]
26	Un-Ku Moon	[3]
27	Randy Mooney	[3]
28	Jarod L. Oatley	[13]
29	Susan Owen	[7]
30	Li-Shiuan Peh	[6] [16]
31	Paul R. Prucnal	[6]
32	Krishna K. Rangan	[10] [21] [24]
33	Ruwan N. S. Ratnayake	[4] [11] [12]
34	Vijay Janapa Reddi	[25] [26] [27]
35	Michael D. Smith	[10] [21] [25] [27]
36	Nikhil Tripathi	[5]
37	Robert J. Wood	[19]

Colors in the list of coauthors