 | 2009 |
| 11 |  | Gerhard Wellein,
Georg Hager,
Thomas Zeiser,
Markus Wittmann,
Holger Fehske:
Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization.
COMPSAC (1) 2009: 579-586 |
| 10 |  | Thomas Zeiser,
Georg Hager,
Gerhard Wellein:
The world's fastest CPU and SMP node: Some performance results from the NEC SX-9.
IPDPS 2009: 1-8 |
| 9 |  | Jan Treibig,
Georg Hager,
Gerhard Wellein:
Multi-core architectures: Complexities of performance prediction and the impact of cache topology
CoRR abs/0910.4865: (2009) |
| 2008 |
| 8 |  | Georg Hager,
Thomas Zeiser,
Gerhard Wellein:
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers.
IPDPS 2008: 1-7 |
| 7 |  | Georg Hager,
Thomas Zeiser,
Gerhard Wellein:
Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems.
Parallel Processing Letters 18(4): 471-490 (2008) |
| 2007 |
| 6 |  | Georg Hager,
Thomas Zeiser,
Gerhard Wellein:
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers
CoRR abs/0712.2302: (2007) |
| 5 |  | Georg Hager,
Holger Stengel,
Thomas Zeiser,
Gerhard Wellein:
RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks
CoRR abs/0712.3389: (2007) |
| 4 |  | Benjamin Bergen,
Gerhard Wellein,
Frank Hülsemann,
Ulrich Rüde:
Hierarchical hybrid grids: achieving TERAFLOP performance on large scale finite element simulations.
IJPEDS 22(4): 311-329 (2007) |
| 2004 |
| 3 |  | Thomas Pohl,
Frank Deserno,
Nils Thürey,
Ulrich Rüde,
Peter Lammers,
Gerhard Wellein,
Thomas Zeiser:
Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures.
SC 2004: 21 |
| 2003 |
| 2 |  | Rolf Rabenseifner,
Gerhard Wellein:
Communication and Optimization Aspects of Parallel Programming Models on Hybrid Architectures.
IJHPCA 17(1): 49-62 (2003) |
| 2002 |
| 1 |  | Gerhard Wellein,
Georg Hager,
Achim Basermann,
Holger Fehske:
Fast Sparse Matrix-Vector Multiplication for TeraFlop/s Computers.
VECPAR 2002: 287-301 |