Gerhard Wellein Coauthor index DBLP Vis pubzone.org

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DBLP keys2009
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGerhard Wellein, Georg Hager, Thomas Zeiser, Markus Wittmann, Holger Fehske: Efficient Temporal Blocking for Stencil Computations by Multicore-Aware Wavefront Parallelization. COMPSAC (1) 2009: 579-586
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLThomas Zeiser, Georg Hager, Gerhard Wellein: The world's fastest CPU and SMP node: Some performance results from the NEC SX-9. IPDPS 2009: 1-8
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJan Treibig, Georg Hager, Gerhard Wellein: Multi-core architectures: Complexities of performance prediction and the impact of cache topology CoRR abs/0910.4865: (2009)
2008
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGeorg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. IPDPS 2008: 1-7
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGeorg Hager, Thomas Zeiser, Gerhard Wellein: Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems. Parallel Processing Letters 18(4): 471-490 (2008)
2007
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGeorg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers CoRR abs/0712.2302: (2007)
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGeorg Hager, Holger Stengel, Thomas Zeiser, Gerhard Wellein: RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks CoRR abs/0712.3389: (2007)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBenjamin Bergen, Gerhard Wellein, Frank Hülsemann, Ulrich Rüde: Hierarchical hybrid grids: achieving TERAFLOP performance on large scale finite element simulations. IJPEDS 22(4): 311-329 (2007)
2004
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLThomas Pohl, Frank Deserno, Nils Thürey, Ulrich Rüde, Peter Lammers, Gerhard Wellein, Thomas Zeiser: Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. SC 2004: 21
2003
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRolf Rabenseifner, Gerhard Wellein: Communication and Optimization Aspects of Parallel Programming Models on Hybrid Architectures. IJHPCA 17(1): 49-62 (2003)
2002
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGerhard Wellein, Georg Hager, Achim Basermann, Holger Fehske: Fast Sparse Matrix-Vector Multiplication for TeraFlop/s Computers. VECPAR 2002: 287-301

Coauthor Index

1Achim Basermann [1]
2Benjamin Bergen [4]
3Frank Deserno [3]
4Holger Fehske [1] [11]
5Georg Hager [1] [5] [6] [7] [8] [9] [10] [11]
6Frank Hülsemann [4]
7Peter Lammers [3]
8Thomas Pohl [3]
9Rolf Rabenseifner [2]
10Ulrich Rüde [3] [4]
11Holger Stengel [5]
12Nils Thürey [3]
13Jan Treibig [9]
14Markus Wittmann [11]
15Thomas Zeiser [3] [5] [6] [7] [8] [10] [11]

Copyright © Sat Nov 28 20:06:51 2009 by Michael Ley (ley@uni-trier.de)