| 2009 | ||
|---|---|---|
| 46 | K. Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, M. Aso, Hiroshi Furukawa: CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104 | |
| 45 | Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara: A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC 2009: 81-86 | |
| 44 | Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009) | |
| 2008 | ||
| 43 | Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen: Power-Aware Testing and Test Strategies for Low Power Devices. DATE 2008 | |
| 42 | Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen: Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266 | |
| 41 | Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael Hsiao, James Chien-Mo Li, Jiun Lang Huang, Ravi Apte: On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 | |
| 40 | Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 | |
| 39 | Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu: VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Design & Test of Computers 25(2): 122-130 (2008) | |
| 38 | Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara: A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits. IEICE Transactions 91-D(3): 667-674 (2008) | |
| 37 | Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy: On Detection of Bridge Defects with Stuck-at Tests. IEICE Transactions 91-D(3): 683-689 (2008) | |
| 36 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electronic Testing 24(4): 379-391 (2008) | |
| 2007 | ||
| 35 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja: Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC 2007: 527-532 | |
| 34 | Nicola Nicolici, Xiaoqing Wen: Embedded Tutorial on Low Power Test. European Test Symposium 2007: 202-210 | |
| 33 | Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo: Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417 | |
| 32 | B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores CoRR abs/0710.4645: (2007) | |
| 31 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Transactions 90-D(9): 1398-1405 (2007) | |
| 2006 | ||
| 30 | Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353 | |
| 29 | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja: Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006 | |
| 28 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita: A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 | |
| 27 | Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006) | |
| 26 | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Transactions 89-D(11): 2756-2765 (2006) | |
| 25 | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Transactions 89-D(5): 1679-1686 (2006) | |
| 2005 | ||
| 24 | Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty: Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC 2005: 59-64 | |
| 23 | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy: On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223 | |
| 22 | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: Path delay test compaction with process variation tolerance. DAC 2005: 845-850 | |
| 21 | B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores. DATE 2005: 860-861 | |
| 20 | Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478 | |
| 19 | Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 | |
| 18 | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 | |
| 17 | Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Transactions 88-D(4): 703-710 (2005) | |
| 16 | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005) | |
| 15 | Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. 20(2): 187-194 (2005) | |
| 14 | Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja: Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electronics 1(3): 319-330 (2005) | |
| 2004 | ||
| 13 | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 | |
| 12 | Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai: VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925 | |
| 2003 | ||
| 11 | Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium 2003: 236-241 | |
| 2001 | ||
| 10 | Xiaoqing Wen, Hsin-Po Wang: A Flexible Logic BIST Scheme and Its Application to SoC Designs. Asian Test Symposium 2001: 463 | |
| 1999 | ||
| 9 | Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto: Random pattern testable design with partial circuit duplication and IDDQ testing. Systems and Computers in Japan 30(5): 18-27 (1999) | |
| 1998 | ||
| 8 | Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: Design for Diagnosability of CMOS Circuits. Asian Test Symposium 1998: 144-149 | |
| 1997 | ||
| 7 | Xiaoqing Wen: Fault Diagnosis for Static CMOS Circuits. Asian Test Symposium 1997: 282-287 | |
| 6 | Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto: Random Pattern Testable Design with Partial Circuit Duplication. Asian Test Symposium 1997: 353-358 | |
| 5 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita: IDDQ test vector selection for transistor short fault testing. Systems and Computers in Japan 28(5): 11-21 (1997) | |
| 1996 | ||
| 4 | Xiaoqing Wen, Kewal K. Saluja: A new method towards achieving global optimality in technology mapping. ICCAD 1996: 9-12 | |
| 1995 | ||
| 3 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita: Transistor leakage fault location with ZDDQ measurement. Asian Test Symposium 1995: 51-57 | |
| 1992 | ||
| 2 | Xiaoqing Wen, Kozo Kinoshita: Testable Designs of Sequential Circuits Under Highly Observable Condition. ITC 1992: 632-641 | |
| 1 | Xiaoqing Wen, Kozo Kinoshita: A Testable Design of Logic Circuits under Highly Observable Condition. IEEE Trans. Computers 41(5): 654-659 (1992) | |