Steven J. E. Wilton

	2012
79		Assem A. M. Bsoul, Steven J. E. Wilton: A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA 2012: 245-254
	2011
78		Scott Y. L. Chin, Steven J. E. Wilton: Towards scalable FPGA CAD through architecture. FPGA 2011: 143-152
77		Joydip Das, Steven J. E. Wilton: An analytical model relating FPGA architecture parameters to routability. FPGA 2011: 181-184
76		Eddie Hung, Steven J. E. Wilton: Speculative Debug Insertion for FPGAs. FPL 2011: 524-531
75		Joydip Das, Steven J. E. Wilton: Accelerated FPGA architecture design: Capabilities and limitations of analytical models. FPT 2011: 1-8
74		Eddie Hung, Steven J. E. Wilton: On evaluating signal selection algorithms for post-silicon debug. ISQED 2011: 290-296
73		Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton: Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48
72		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. VLSI Syst. 19(12): 2195-2208 (2011)
71		Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. VLSI Syst. 19(12): 2229-2242 (2011)
	2010
70		Steven J. E. Wilton: Towards Analytical Methods for FPGA Architecture Investigation. ARC 2010: 3
69		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272
68		Assem A. M. Bsoul, Steven J. E. Wilton: An FPGA architecture supporting dynamically controlled power gating. FPT 2010: 1-8
67		Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt: Accelerating trace computation in post-silicon debug. ISQED 2010: 244-249
66		Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward: Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 816-829 (2010)
	2009
65		Xiongfei Meng, Resve Saleh, Steven J. E. Wilton: Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC 2009: 25-28
64		Alastair M. Smith, Steven J. E. Wilton, Joydip Das: Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA 2009: 181-190
63		Scott Y. L. Chin, Steven J. E. Wilton: An analytical model relating FPGA architecture and place and route runtime. FPL 2009: 146-153
62		Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: Modeling post-techmapping and post-clustering FPGA circuit depth. FPL 2009: 205-211
61		Scott Y. L. Chin, Steven J. E. Wilton: Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL 2009: 717-718
60		Sohaib Majzoub, Resve Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward: Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC 2009: 357-360
59		Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Floating-Point FPGA: Architecture and Modeling. IEEE Trans. VLSI Syst. 17(12): 1709-1718 (2009)
58		Bradley R. Quinton, Steven J. E. Wilton: Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. VLSI Syst. 17(9): 1334-1339 (2009)
57		Scott Y. L. Chin, Steven J. E. Wilton: Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. TRETS 1(4): (2009)
	2008
56		Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang: BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD 2008: 1-10
55		Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226
54		Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232
53		Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton: BackSpace: Moving Towards Reality. MTV 2008: 49-54
52		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
51		Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Practical Asynchronous Interconnect Network Design. IEEE Trans. VLSI Syst. 16(5): 579-588 (2008)
50		Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfig. Comp. 2008: (2008)
49		Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfig. Comp. 2008: (2008)
48		Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk: A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. TRETS 1(1): (2008)
47		Julien Lamoureux, Steven J. E. Wilton: On the trade-off between power and flexibility of FPGA clock networks. TRETS 1(3): (2008)
	2007
46		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
45		Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton: A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41
44		Julien Lamoureux, Steven J. E. Wilton: Clock-Aware Placement for FPGAs. FPL 2007: 124-131
43		Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201
42		Bradley R. Quinton, Steven J. E. Wilton: Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL 2007: 202-209
	2006
41		Steven J. E. Wilton, André DeHon: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 ACM 2006
40		Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo: Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44
39		Julien Lamoureux, Steven J. E. Wilton: FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108
38		Julien Lamoureux, Steven J. E. Wilton: Architecture and CAD for FPGA Clock Networks. FPL 2006: 1-2
37		Julien Lamoureux, Steven J. E. Wilton: Activity Estimation for Field-Programmable Gate Arrays. FPL 2006: 1-8
36		Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL 2006: 1-8
35		Andy Yan, Steven J. E. Wilton: Product-Term-Based Synthesizable Embedded Programmable Logic Cores. IEEE Trans. VLSI Syst. 14(5): 474-488 (2006)
	2005
34		Herman Schmit, Steven J. E. Wilton: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005 ACM 2005
33		Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005 IEEE 2005
32		Zion Kwok, Steven J. E. Wilton: Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. FCCM 2005: 35-44
31		Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180
30		Bradley R. Quinton, Steven J. E. Wilton: Post-Silicon Debug Using Programmable Logic Cores. FPT 2005: 241-248
29		Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274
28		Bradley R. Quinton, Steven J. E. Wilton: Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) 2005: 45-48
27		Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton: Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90
26		Kara K. W. Poon, Steven J. E. Wilton, Andy Yan: A detailed power model for field-programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 10(2): 279-302 (2005)
25		Peter Hallschmid, Steven J. E. Wilton: Routing architecture optimizations for high-density embedded programmable IP cores. IEEE Trans. VLSI Syst. 13(11): 1320-1324 (2005)
24		S. W. Oldridge, Steven J. E. Wilton: A novel FPGA architecture supporting wide, shallow memories. IEEE Trans. VLSI Syst. 13(6): 758-762 (2005)
23		Julien Lamoureux, Steven J. E. Wilton: On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electronics 1(2): 119-132 (2005)
	2004
22		Steven J. E. Wilton, Su-Shin Ang, Wayne Luk: The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728
21		Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux: An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) 2004: 885-888
	2003
20		Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton: Architectures and algorithms for synthesizable embedded programmable logic cores. FPGA 2003: 3-11
19		Julien Lamoureux, Steven J. E. Wilton: On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD 2003: 701-708
	2002
18		Andy Yan, Rebecca Cheng, Steven J. E. Wilton: On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. FPGA 2002: 147-156
17		Kara K. W. Poon, Andy Yan, Steven J. E. Wilton: A Flexible Power Model for FPGAs. FPL 2002: 312-321
	2001
16		Steven J. E. Wilton: A crosstalk-aware timing-driven router for FPGAs. FPGA 2001: 21-28
15		Peter Hallschmid, Steven J. E. Wilton: Detailed routing architectures for embedded programmable logic IP cores. FPGA 2001: 69-74
14		Ernie Lin, Steven J. E. Wilton: Macrocell Architectures for Product Term Embedded Memory Arrays. FPL 2001: 48-58
13		Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. VLSI Syst. 9(1): 223-226 (2001)
	2000
12		Steven J. E. Wilton: Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. FPGA 2000: 67-74
11		Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh: FPGA Implementation of a Prototype WDM On-Line Scheduler. FPL 2000: 773-776
10		Steven J. E. Wilton: Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 56-68 (2000)
	1999
9		William K. C. Ho, Steven J. E. Wilton: Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. FPL 1999: 111-123
8		M. Imran Masud, Steven J. E. Wilton: A New Switch Block for Segmented FPGAs. FPL 1999: 274-281
7		Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. VLSI Syst. 7(1): 80-91 (1999)
	1998
6		Steven J. E. Wilton: SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. FPGA 1998: 171-178
	1997
5		Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16
	1995
4		Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103
	1994
3		Norman P. Jouppi, Steven J. E. Wilton: Tradeoffs in Two-Level On-Chip Caching. ISCA 1994: 34-45
	1993
2		Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948
1		Steven J. E. Wilton, Zvonko G. Vranesic: Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55

Coauthor Index

1	Tor M. Aamodt	[67]
2	Usman Ahmed	[69] [72]
3	Su-Shin Ang	[22]
4	Kimberly Bozman	[20]
5	Assem A. M. Bsoul	[68] [79]
6	John Chappel	[2]
7	Rebecca Cheng	[18]
8	Winnie W. Cheng	[11]
9	Scott Y. L. Chin	[36] [50] [57] [61] [63] [78]
10	Gary Chun Tak Chow	[31]
11	Paul Chow	[2]
12	Joydip Das	[62] [64] [71] [75] [77]
13	André DeHon	[41]
14	Gennady Feygin	[2]
15	Jeffrey B. Goeders	[73]
16	Grant Goodes	[2]
17	Marcel Gort	[53] [56]
18	Mark R. Greenstreet	[29] [51]
19	P. Glenn Gulak	[2]
20	Oswin Hall	[2]
21	Peter Hallschmid	[15] [25]
22	Babak Hamidzadeh	[11]
23	Lei He	[27]
24	Chun Hok Ho	[40] [43] [45] [48] [54] [59]
25	William K. C. Ho	[9]
26	Alan J. Hu	[53] [56]
27	Eddie Hung	[74] [76]
28	Michael Hutton (Michael D. Hutton, Mike Hutton)	[27]
29	Christopher W. Jones	[21]
30	Norman P. Jouppi	[3]
31	Noha Kafafi	[20]
32	Johnny J. W. Kuan	[67]
33	Zion Kwok	[32]
34	Andrew Lam	[55] [71]
35	Julien Lamoureux	[19] [21] [23] [37] [38] [39] [44] [46] [47] [49] [52]
36	Clarence S. P. Lee	[36] [50]
37	Guy Lemieux (Guy G. Lemieux, Guy G. F. Lemieux)	[46] [52] [69] [72] [73]
38	Philip Heng Wai Leong	[31] [33] [40] [43] [45] [48] [49] [54] [55] [59] [62] [71]
39	Ernie Lin	[14]
40	Sergio López-Buedo	[40]
41	Wayne Luk	[22] [31] [40] [43] [45] [48] [49] [54] [55] [59] [62] [71]
42	Sohaib Majzoub	[60] [66]
43	M. Imran Masud	[8]
44	Xiongfei Meng	[65]
45	S. W. Oldridge	[24]
46	Flavio M. de Paula	[53] [56]
47	Kara K. W. Poon	[17] [26]
48	Bradley R. Quinton	[28] [29] [30] [42] [45] [48] [51] [58]
49	Tero Rissa	[33]
50	Jonathan Rose	[4] [5] [7] [13]
51	Resve A. Saleh (Resve Saleh, Res Saleh)	[60] [65] [66]
52	Ahmad Sayes	[2]
53	Herman Schmit	[34]
54	Satwant Singh	[2]
55	Alastair M. Smith	[64]
56	Michael B. Smith	[2]
57	L. S. M. Tsui	[31]
58	Tim Tuan	[27]
59	Zvonko G. Vranesic	[1] [4] [5] [7] [13]
60	Rabab Kreidieh Ward (Rabab K. Ward)	[60] [66]
61	Andy Yan	[17] [18] [26] [35]
62	Jin Yang	[56]
63	Chi Wai Yu	[43] [49] [59]

Colors in the list of coauthors

Last update Sat May 26 02:31:23 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page