 | 2009 |
|---|
| 12 |       | Konstantin Moiseev,
Avinoam Kolodny,
Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing.
ACM Trans. Design Autom. Electr. Syst. 14(4): (2009) |
| 2008 |
|---|
| 11 | | Konstantin Moiseev,
Avinoam Kolodny,
Shmuel Wimer:
Timing-aware power-optimal ordering of signals.
ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) |
| 10 | | Konstantin Moiseev,
Shmuel Wimer,
Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles.
Integration 41(2): 253-268 (2008) |
| 2006 |
|---|
| 9 | | Konstantin Moiseev,
Shmuel Wimer,
Avinoam Kolodny:
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.
ISCAS 2006 |
| 1993 |
|---|
| 8 | | Shmuel Wimer,
Israel Koren,
Israel Cederbaum:
On Paths with the Shortest Average Arc Length in Weighted Graphs.
Discrete Applied Mathematics 45(2): 169-179 (1993) |
| 7 | | Jack A. Feldman,
Israel A. Wagner,
Shmuel Wimer:
An efficient algorithm for some multirow layout problems.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1178-1185 (1993) |
| 1992 |
|---|
| 6 |  | Israel Cederbaum,
Israel Koren,
Shmuel Wimer:
Balanced Block Spacing for VLSI Layout.
Discrete Applied Mathematics 40(3): 303-318 (1992) |
| 1989 |
|---|
| 5 | | Shmuel Wimer,
Israel Koren,
Israel Cederbaum:
Optimal aspect ratios of building blocks in VLSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 139-145 (1989) |
| 4 | | Reuven Bar-Yehuda,
Jack A. Feldman,
Ron Y. Pinter,
Shmuel Wimer:
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(7): 737-743 (1989) |
| 1988 |
|---|
| 3 | | Shmuel Wimer,
Israel Koren,
Israel Cederbaum:
Optimal Aspect Ratios of Building Blocks in VLSI.
DAC 1988: 66-72 |
| 2 | | Shmuel Wimer,
Israel Koren:
Analysis of strategies for constructive general block placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 371-377 (1988) |
| 1987 |
|---|
| 1 | | Shmuel Wimer,
Ron Y. Pinter,
Jack A. Feldman:
Optimal Chaining of CMOS Transistors in a Functional Cell.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 795-801 (1987) |
