Zhaojun Wo

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2005

5 Zhaojun Wo, Israel Koren: Effective analytical delay model for transistor sizing. ASP-DAC 2005: 387-392

4 Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20

3 Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: Yield-aware Floorplanning. DSD 2005: 247-253

2 Zhaojun Wo, Israel Koren: Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters. IEEE Symposium on Computer Arithmetic 2005: 114-121

1 Zhaojun Wo, Israel Koren: Technology Mapping for Reliability Enhancement in Logic Synthesis. ISQED 2005: 137-142

	2005
5		Zhaojun Wo, Israel Koren: Effective analytical delay model for transistor sizing. ASP-DAC 2005: 387-392
4		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: An ILP Formulation for Yield-driven Architectural Synthesis. DFT 2005: 12-20
3		Zhaojun Wo, Israel Koren, Maciej J. Ciesielski: Yield-aware Floorplanning. DSD 2005: 247-253
2		Zhaojun Wo, Israel Koren: Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters. IEEE Symposium on Computer Arithmetic 2005: 114-121
1		Zhaojun Wo, Israel Koren: Technology Mapping for Reliability Enhancement in Logic Synthesis. ISQED 2005: 137-142

Coauthor Index

1	Maciej J. Ciesielski	[3] [4]
2	Israel Koren	[1] [2] [3] [4] [5]