Justin S. Wong

	2009
4		Justin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung: Self-Measurement of Combinatorial Circuit Delays in FPGAs. TRETS 2(2): (2009)
	2008
3		N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Measuring and modeling FPGA clock variability. FPGA 2008: 258
2		Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole: Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704
1		N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328

Coauthor Index

1	Peter Y. K. Cheung	[1] [2] [3] [4]
2	N. Pete Sedcole	[1] [2] [3] [4]