Allen C.-H. Wu

	2007
51		Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 564-573 (2007)
	2006
50		Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006
49		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006)
48		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. VLSI Syst. 14(1): 81-85 (2006)
	2005
47		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314
46		Bing-Fei Wu, Chuan-Tsai Lin, Chao-Jung Chen, Tze-Chiuan Lai, Hsueh-Lung Liao, Allen C.-H. Wu: A fast lane and vehicle detection approach for autonomous vehicles. SIP 2005: 305-310
	2004
45		Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665
	2003
44		Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103
43		Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135
	2002
42		M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu: A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. ISCAS (1) 2002: 81-84
41		J. C.-Y. Kao, C.-F. Su, Allen C.-H. Wu: High-performance FIR generation based on a timing-driven architecture and component selection method. ISCAS (4) 2002: 759-762
	2001
40		Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu: An RTL design-space exploration method for high-level applications. ASP-DAC 2001: 162-168
	2000
39		Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud: Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42
38		Chien-Chu Kuo, Allen C.-H. Wu: Delay Budgeting for a Timing-Closure-Driven Design Method. ICCAD 2000: 202-207
37		Wen-Jong Fang, Allen C.-H. Wu: Multiway FPGA partitioning by fully exploiting design hierarchy. ACM Trans. Design Autom. Electr. Syst. 5(1): 34-50 (2000)
36		Chi-Hong Hwang, Allen C.-H. Wu: A predictive system shutdown method for energy saving of event-driven computation. ACM Trans. Design Autom. Electr. Syst. 5(2): 226-241 (2000)
35		Allen C.-H. Wu, Nikil D. Dutt: Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98). IEEE Trans. VLSI Syst. 8(5): 469-471 (2000)
	1999
34		Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu: A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. ASP-DAC 1999: 351-354
33		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. DAC 1999: 262-267
32		Kun-Ming Ho, Allen C.-H. Wu: Module Generation of High Performance FPGA-Based Multipliers. FPGA 1999: 251
31		Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen: EmGen-a module generator for logic emulation applications. IEEE Trans. VLSI Syst. 7(4): 488-492 (1999)
30		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 475-483 (1999)
	1998
29		Wen-Jong Fang, Allen C.-H. Wu: Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. DAC 1998: 283-286
28		Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin: Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. ISPD 1998: 12-17
27		Wen-Jong Fang, Allen C.-H. Wu: Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs. IEEE Design & Test of Computers 15(2): 65-72 (1998)
	1997
26		Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen: A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. DAC 1997: 101-106
25		Wen-Jong Fang, Allen C.-H. Wu: Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. DAC 1997: 518-521
24		Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen: Module Generation of Complex Macros for Logic-Emulation Applications. FPGA 1997: 69-75
23		Chi-Hong Hwang, Allen C.-H. Wu: A predictive system shutdown method for energy saving of event-driven computation. ICCAD 1997: 28-32
22		Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin: Preserving HDL synthesis hierarchy for cell placement. ISPD 1997: 169-174
21		Yann-Rue Lin, Cheng-Tsung Hwang, Allen C.-H. Wu: Scheduling techniques for variable voltage low power designs. ACM Trans. Design Autom. Electr. Syst. 2(2): 81-97 (1997)
20		Wen-Jong Fang, Allen C.-H. Wu: A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1188-1195 (1997)
19		Yuh-Sheng Lee, Allen C.-H. Wu: A performance and routability-driven router for FPGAs considering path delays. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 179-185 (1997)
	1996
18		Wen-Jong Fang, Allen C.-H. Wu: A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. ICCAD 1996: 638-643
17		Tsing-Gen Lee, Wen-Jong Fang, Allen C.-H. Wu: The Design and Inplementation of a Cooperative Design-view Environment for Interactive Partitioning Applications. Softw., Pract. Exper. 26(10): 1141-1160 (1996)
	1995
16		Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee: EMPAR: an interactive synthesis environment for hardware emulations. ASP-DAC 1995
15		Yuh-Sheng Lee, Allen C.-H. Wu: A Performance and Routability Driven Router for FPGAs Considering Path Delays. DAC 1995: 557-561
14		Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin: TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 371-374 (1995)
13		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
	1994
12		Tsung-Yi Wu, Tzu-Chieh Tien, Allen C.-H. Wu, Youn-Long Lin: A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. EDAC-ETC-EUROASIC 1994: 277-281
11		Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
10		Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski: A transformation-based method for loop folding. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 439-450 (1994)
	1993
9		Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
	1992
8		Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin: An effective methodology for functional pipelining. ICCAD 1992: 230-233
7		Allen C.-H. Wu, Tedd Hadley, Daniel Gajski: An efficient multi-view design model for real-time interactive synthesis. ICCAD 1992: 328-331
6		Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul: Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361
5		Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu: Layout placement for sliced architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 102-114 (1992)
4		Allen C.-H. Wu, Daniel D. Gajski: Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 453-463 (1992)
	1991
3		Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski: Layout-Area Models for High-Level Synthesis. ICCAD 1991: 34-37
	1990
2		Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski: A new algorithm for transistor sizing in CMOS circuits. EURO-DAC 1990: 589-593
1		Allen C.-H. Wu, Daniel Gajski: Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD 1990: 144-147

Coauthor Index

1	Pierre Bricaud	[39]
2	Viraphol Chaiyakul	[3] [6] [39]
3	Alex C.-Y. Chang	[42] [43]
4	Chao-Jung Chen	[46]
5	Chau-Shen Chen	[9] [13]
6	Ching-Dong Chen	[14]
7	Duan-Ping Chen	[24] [31]
8	Yi-Ling Chiang	[50] [51]
9	Nikil D. Dutt (Nikil Dutt)	[35]
10	Wen-Jong Fang	[16] [17] [18] [20] [22] [24] [25] [26] [27] [29] [31] [34] [37]
11	Daniel Gajski (Daniel D. Gajski)	[1] [2] [3] [4] [5] [6] [7] [8] [10] [39]
12	Tedd Hadley	[7]
13	Kun-Ming Ho	[32]
14	Chih-Kuang Hsieh	[40]
15	Cheng-Tsung Hwang	[21]
16	Chi-Hong Hwang	[23] [36]
17	TingTing Hwang	[9] [11] [13] [43] [44] [45] [47] [48] [49] [50] [51]
18	J. C.-Y. Kao	[41]
19	Peng-Cheng Kao	[34] [40]
20	Chien-Chu Kuo	[38]
21	Wu-An Kuo	[43] [44] [45] [47] [48] [49] [50] [51]
22	Fadi J. Kurdahi	[6]
23	Tze-Chiuan Lai	[46]
24	Lawrence L. Larmore	[5]
25	Tsing-Fa Lee	[8] [10]
26	Tsing-Gen Lee	[16] [17]
27	Yuh-Sheng Lee	[14] [15] [19]
28	Hsueh-Lung Liao	[46]
29	M.-J. Liao	[42]
30	Chuan-Tsai Lin	[46]
31	Yann-Rue Lin	[21]
32	Youn-Long Lin	[8] [9] [10] [11] [12] [13] [14] [22] [28] [30] [33]
33	Jennifer Y.-L. Lo	[44]
34	Shojiro Mori	[39]
35	Tom Nukiyama	[39]
36	Champaka Ramachandran	[6]
37	C.-F. Su	[41] [42]
38	Hsiao-Pin Su	[28] [30] [33]
39	Tzu-Chieh Tien	[12]
40	Yu-Wen Tsay	[9] [13] [22]
41	Kuo-Hua Wang	[11]
42	Wen-Sing Wang	[11]
43	Bing-Fei Wu	[46]
44	Tsung-Yi Wu	[12]
45	Ti-Yen Yen	[26]
46	Nels Vander Zanden	[2]

Colors in the list of coauthors