An-Yeu Wu

	2009
50		Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu: A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. ASP-DAC 2009: 121-122
	2008
49		Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu: Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. ISCAS 2008: 3150-3153
48		Huifei Rao, Jie Chen, V. H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu: An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. ISCAS 2008: 608-611
47		Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Low-power traceback MAP decoding for double-binary convolutional turbo decoder. ISCAS 2008: 736-739
46		Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu: Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks. SiPS 2008: 200-203
45		Chih-Hao Chao, Chun-Yuan Chu, An-Yeu Wu: Location-Constrained Particle Filter human positioning and tracking system. SiPS 2008: 73-76
44		Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu: High-throughput dual-mode single/double binary map processor design for wireless wan. SiPS 2008: 83-87
43		Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu: Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks. IEEE Trans. Computers 57(9): 1156-1168 (2008)
42		Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. IEEE Trans. VLSI Syst. 16(10): 1358-1371 (2008)
41		I-Chyn Wey, You-Gang Chen, An-Yeu Wu: Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. VLSI Syst. 16(12): 1708-1712 (2008)
40		Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu: Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme. Signal Processing Systems 52(1): 59-73 (2008)
	2007
39		Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien: A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. ISCAS 2007: 1113-1116
38		Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao: Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. ISCAS 2007: 1803-1806
37		Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu: Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS 2007: 869-872
36		Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu: A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. NOCS 2007: 317-322
35		Tzu-Hao Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, An-Yeu Wu: Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. SiPS 2007: 187-192
34		Kai-Yuan Jheng, Yuan-Jyue Chen, An-Yeu Wu: Multilevel Linc System Design for Power Efficiency Enhancement. SiPS 2007: 31-34
33		Chun-Yuan Chu, Jyh-Ting Lai, An-Yeu Wu: Robust Packet Detector based Automatic Gain Control Algorithm for OFDM-based Ultra-WideBand systems. SiPS 2007: 403-406
32		Chi-Li Yu, Tzu-Hao Yu, An-Yeu Wu: On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm. SiPS 2007: 430-435
31		Sung-Tze Wu, Chih-Hao Chao, I-Chyn Wey, An-Yeu Wu: Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. SiPS 2007: 493-498
30		Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee: Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. VLSI Syst. 15(2): 236-240 (2007)
29		Fan-Min Li, An-Yeu Wu: On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold. IEEE Transactions on Signal Processing 55(11): 5506-5516 (2007)
	2006
28		Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS 2006
27		Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu: A portable all-digital pulsewidth control loop for SOC applications. ISCAS 2006
26		Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao: DSP engine design for LINC wireless transmitter systems. ISCAS 2006
25		Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen: A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 165-170
24		Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen: A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. SiPS 2006: 171-176
23		Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu: A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. SiPS 2006: 309-312
22		Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu: On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. SiPS 2006: 422-427
21		Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu: Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems. SiPS 2006: 62-65
20		Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. SiPS 2006: 89-94
	2005
19		Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu: A memory-reduced log-MAP kernel for turbo decoder. ISCAS (2) 2005: 1032-1035
18		I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu: A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) 2005: 1074-1077
17		Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A scalable DCO design for portable ADPLL designs. ISCAS (6) 2005: 5449-5452
16		Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu: Digital signal processing engine design for polar transmitter in wireless communication systems. ISCAS (6) 2005: 6026-6029
15		Chih-Hsiu Lin, An-Yeu Wu: Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture. IEEE Transactions on Signal Processing 53(8-2): 3325-3336 (2005)
	2004
14		Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu: Least squares approximation-based ROM-free direct digital frequency synthesizer. ISCAS (2) 2004: 701-704
13		Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu: VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. ISCAS (2) 2004: 773-776
12		Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu: 1000BASE-T Gigabit Ethernet baseband DSP IC design. ISCAS (4) 2004: 401-404
11		Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu: A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ISCAS (5) 2004: 293-296
10		Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai: High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. IEEE Trans. VLSI Syst. 12(2): 218-226 (2004)
	2003
9		Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu: Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems. ISCAS (2) 2003: 121-124
8		Huai-Yi Hsu, Sheng-Feng Wang, An-Yeu Wu: A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm. VLSI Signal Processing 34(3): 251-259 (2003)
	2002
7		Meng-Da Yang, An-Yeu Wu: A new pipelined adaptive DFE architecture with improved convergence rate. ISCAS (4) 2002: 213-216
6		Cheng-Shing Wu, An-Yeu Wu: A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. ISCAS (5) 2002: 453-456
	2001
5		Chi-Li Yu, An-Yeu Wu: An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. ISCAS (4) 2001: 250-253
	1998
4		An-Yeu Wu, K. J. Ray Liu: Algorithm-based low-power transform coding architectures: the multirate approach. IEEE Trans. VLSI Syst. 6(4): 707-718 (1998)
	1995
3		An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu: Parallel programmable video co-processor design. ICIP 1995: 61-64
	1994
2		An-Yeu Wu, K. J. Ray Liu: A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. ISCAS 1994: 155-158
	1993
1		K. J. Ray Liu, An-Yeu Wu: A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. ISCAS 1993: 1999-2002

Coauthor Index

1	Woon Tiong Ang	[38] [48]
2	Lung-Hao Chang	[18]
3	Shih-Hung Chang	[18]
4	Chih-Hao Chao	[31] [36] [39] [43] [45]
5	Chun-Yu Chen	[44] [47]
6	Jie Chen	[38] [48]
7	Nancy Fang-Yih Chen	[12]
8	Wen-Chiang Chen	[24] [25]
9	Yen-Liang Chen	[23] [40] [49]
10	You-Gang Chen	[18] [37] [41]
11	Yuan-Jyue Chen	[34]
12	Weber Chien	[39]
13	Chun-Yuan Chu	[24] [25] [33] [45]
14	Chih-Liang Ding	[35]
15	Huai-Yi Hsu	[8] [14]
16	Ming-Feng Hsu	[23] [40]
17	Chun-Hsiang Huang	[43]
18	Kai Huang	[13]
19	Keng-Hsien Huang	[43]
20	Kuo-Ken Huang	[21]
21	Kai-Yuan Jheng	[11] [22] [23] [26] [34]
22	Shyh-Jye Jou	[11]
23	Hung Yang Ko	[14] [16]
24	Jen-Chih Kuo	[9]
25	Yen-Lin Kuo	[39]
26	Jyh-Ting Lai	[10] [12] [24] [25] [30] [33] [40]
27	Chien-Hsiung Lee	[30]
28	Yu-Hung Lee	[21]
29	Fan-Min Li	[13] [20] [29] [42]
30	Pai-Chi Li	[35]
31	Yu-Kuang Lien	[36]
32	Cheng-Hung Lin	[19] [20] [42] [44] [47] [50]
33	Chih-Hsiu Lin	[15]
34	Hsiu-Ping Lin	[12]
35	Shu-Yen Lin	[43] [46]
36	Ting-Jung Lin	[46]
37	K. J. Ray Liu	[1] [2] [3] [4]
38	Shang-Chieh Liu	[3]
39	Arun Raghupathy	[3]
40	Huifei Rao	[38] [48]
41	Pei-Ling Shen	[13]
42	Wein-Tsung Shen	[36]
43	Xin-Yu Shih	[50]
44	Shih-Yu Sun	[35]
45	Tsung-Han Tsai	[19]
46	Hen-Wai Tsao	[26]
47	Sheng-Feng Wang	[8]
48	Wei Wang	[17] [27] [28]
49	Yi-Chiuan Wang	[16] [26]
50	Ching-Hua Wen	[9] [14]
51	I-Chyn Wey	[17] [18] [27] [28] [31] [37] [38] [41] [48]
52	Cheng-Shing Wu	[6]
53	Chia-Tsun Wu	[17] [27] [28]
54	Sung-Tze Wu	[31]
55	Meng-Da Yang	[7] [10]
56	Jhao-Ji Ye	[37]
57	Changhong Yu	[38]
58	Chi-Li Yu	[5] [22] [32]
59	Tzu-Hao Yu	[21] [22] [32] [35]
60	Cheng-Zhou Zhan	[49] [50]
61	Hong Zhao	[38]
62	V. H. Zhao	[48]

Colors in the list of coauthors