Lifeng Wu

	2009
13		Duo Li, Sheldon X.-D. Tan, Lifeng Wu: Hierarchical Krylov subspace based reduction of large interconnects. Integration 42(2): 193-202 (2009)
	2008
12		Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu: Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. ICCAD 2008: 744-749
	2007
11		Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He: TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1382-1392 (2007)
	2006
10		Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu: Compact Reduced Order Modeling for Multiple-Port Interconnects. ISQED 2006: 413-418
9		Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006)
	2005
8		Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu: Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093
7		Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175
6		Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547
	2003
5		Lifeng Wu: NBTI/HCI Modeling and Full-Chip Analysis in Design Environment. ISQED 2003: 13-14
	2001
4		Lifeng Wu, Zhihong Liu: Full-Chip Reliability Simulation for VDSM Integrated Circuits. Microelectronics Reliability 41(9-10): 1273-1278 (2001)
	2000
3		Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu: Gate-level aged timing simulation methodology for hot-carrier reliability assurance. ASP-DAC 2000: 289-294
2		Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami: GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. ISQED 2000: 73-80
	1991
1		Lifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li: GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process. DAC 1991: 585-590

Coauthor Index

1	Yici Cai	[6] [7] [8] [9]
2	Alvin I-Hsien Chen	[2] [3]
3	Gengsheng Chen	[12]
4	Ping Chen	[2] [3]
5	Jeffrey Fan	[9]
6	Jingkun Fang	[2] [3]
7	Lei He	[11]
8	Xianlong Hong	[6] [7] [8] [9]
9	Wenting Hou	[8]
10	Nobufusa Iwanishi	[2] [3]
11	Yoshiyuki Kawakami	[2] [3]
12	Norio Koike	[2] [3]
13	Duo Li	[13]
14	Hang Li	[6] [7] [9]
15	Zhijian Li	[1]
16	Pu Liu	[10] [11]
17	Zhihong Liu	[2] [3] [4]
18	Bruce McGaughy	[10] [11]
19	Yoshifumi Okamoto	[2]
20	Zhu Pan	[8]
21	Zhenyu Qi	[6] [7] [9]
22	Sheldon X.-D. Tan (Xiang-Dong Tan)	[6] [7] [8] [9] [10] [11] [12] [13]
23	Boyuan Yan	[12]
24	Heting Yan	[2]
25	Zhilian Yang	[1]
26	Chune-Sin Yeh	[2] [3]
27	Hirokazu Yonezawa	[2] [3]
28	Zhiping Yu	[1]

Colors in the list of coauthors