| 2008 |
|---|
| 9 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Shianling Wu,
Zhigang Wang,
Zhigang Jiang,
Boryau Sheu,
Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers 25(2): 122-130 (2008) |
| 2007 |
|---|
| 8 | EE | B. Cheon,
E. Lee,
Laung-Terng Wang,
Xiaoqing Wen,
P. Hsu,
J. Cho,
J. Park,
H. Chao,
Shianling Wu:
At-Speed Logic BIST for IP Cores
CoRR abs/0710.4645: (2007) |
| 2005 |
|---|
| 7 | EE | B. Cheon,
E. Lee,
Laung-Terng Wang,
Xiaoqing Wen,
P. Hsu,
J. Cho,
J. Park,
H. Chao,
Shianling Wu:
At-Speed Logic BIST for IP Cores.
DATE 2005: 860-861 |
| 6 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Po-Ching Hsu,
Shianling Wu,
Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs.
ICCD 2005: 475-478 |
| 2004 |
|---|
| 5 | EE | Laung-Terng Wang,
Khader S. Abdel-Hafez,
Shianling Wu,
Xiaoqing Wen,
Hiroshi Furukawa,
Fei-Sheng Hsu,
Shyh-Horng Lin,
Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
ITC 2004: 916-925 |
| 2000 |
|---|
| 4 | EE | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Jing-Yang Jou,
Li-C. Wang,
Chi-Feng Wu,
Shianling Wu:
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium 2000: 17- |
| 1998 |
|---|
| 3 | EE | Carlos G. Parodi,
Vishwani D. Agrawal,
Michael L. Bushnell,
Shianling Wu:
A non-enumerative path delay fault simulator for sequential circuits.
ITC 1998: 934-943 |
| 1996 |
|---|
| 2 | EE | Najmi T. Jarwala,
Paul W. Rutkowski,
Shianling Wu,
Chi W. Yau:
Lessons Learned from Practical Applications of BIST/B-S Technology.
Asian Test Symposium 1996: 251-257 |
| 1985 |
|---|
| 1 | | Sivanarayana Mallela,
Shianling Wu:
A Sequential Circuit Test Generation System.
ITC 1985: 57-61 |
