| 2009 | ||
|---|---|---|
| 11 | Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009) | |
| 2008 | ||
| 10 | Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael Hsiao, James Chien-Mo Li, Jiun Lang Huang, Ravi Apte: On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151 | |
| 9 | Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu: VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Design & Test of Computers 25(2): 122-130 (2008) | |
| 2007 | ||
| 8 | B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores CoRR abs/0710.4645: (2007) | |
| 2005 | ||
| 7 | B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores. DATE 2005: 860-861 | |
| 6 | Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478 | |
| 2004 | ||
| 5 | Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai: VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925 | |
| 2000 | ||
| 4 | Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17- | |
| 1998 | ||
| 3 | Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943 | |
| 1996 | ||
| 2 | Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau: Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium 1996: 251-257 | |
| 1985 | ||
| 1 | Sivanarayana Mallela, Shianling Wu: A Sequential Circuit Test Generation System. ITC 1985: 57-61 | |