Shianling Wu

	2009
11		Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li: Turbo1500: Core-Based Design for Test and Diagnosis. IEEE Design & Test of Computers 26(1): 26-35 (2009)
	2008
10		Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael Hsiao, James Chien-Mo Li, Jiun Lang Huang, Ravi Apte: On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. DFT 2008: 143-151
9		Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu: VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. IEEE Design & Test of Computers 25(2): 122-130 (2008)
	2007
8		B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores CoRR abs/0710.4645: (2007)
	2005
7		B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu: At-Speed Logic BIST for IP Cores. DATE 2005: 860-861
6		Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo: At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478
	2004
5		Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai: VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ITC 2004: 916-925
	2000
4		Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-
	1998
3		Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943
	1996
2		Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau: Lessons Learned from Practical Applications of BIST/B-S Technology. Asian Test Symposium 1996: 251-257
	1985
1		Sivanarayana Mallela, Shianling Wu: A Sequential Circuit Test Generation System. ITC 1985: 57-61

Coauthor Index

1	Khader S. Abdel-Hafez	[5]
2	Vishwani D. Agrawal	[3] [4]
3	Ravi Apte	[10] [11]
4	Michael L. Bushnell	[3]
5	H. Chao	[7] [8]
6	Hao-Jan Chao	[11]
7	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[4]
8	B. Cheon	[7] [8]
9	J. Cho	[7] [8]
10	Hiroshi Furukawa	[5]
11	Xinli Gu	[9]
12	Jianghao Guo	[11]
13	Jonhson Guo	[6]
14	Michael Hsiao	[10]
15	Fei-Sheng Hsu	[5]
16	P. Hsu	[7] [8]
17	Po-Ching Hsu	[6]
18	Jiun Lang Huang	[10]
19	Najmi T. Jarwala	[2]
20	Zhigang Jiang	[9] [10]
21	Wen-Ben Jone	[11]
22	Jing-Yang Jou	[4]
23	E. Lee	[7] [8]
24	Kuen-Jong Lee	[11]
25	Chien-Mo James Li (James Chien-Mo Li)	[10]
26	Fangfang Li	[11]
27	Shyh-Horng Lin	[5]
28	Jinsong Liu	[11]
29	Sivanarayana Mallela	[1]
30	Yanlong Niu	[11]
31	J. Park	[7] [8]
32	Carlos G. Parodi	[3]
33	Paul W. Rutkowski	[2]
34	Boryau Sheu	[9] [10] [11]
35	Jiayong Song	[10]
36	Yi-Chih Sung	[11]
37	Sen-Wei Tsai	[5]
38	Chi-Chun Wang	[11]
39	Laung-Terng Wang	[5] [6] [7] [8] [9] [10] [11]
40	Li-C. Wang	[4]
41	Wei-Shin Wang	[11]
42	Zhigang Wang	[9]
43	Xiaoqing Wen	[5] [6] [7] [8] [9] [10] [11]
44	Chi-Feng Wu	[4]
45	Chi W. Yau	[2]

Colors in the list of coauthors