 | 2009 |
|---|
| 11 |       | Xiaoxia Wu,
Jian Li,
Lixin Zhang,
Evan Speight,
Yuan Xie:
Power and performance of read-write aware Hybrid Caches with non-volatile memories.
DATE 2009: 737-742 |
| 10 | | Xiaoxia Wu,
Jian Li,
Lixin Zhang,
Evan Speight,
Ramakrishnan Rajamony,
Yuan Xie:
Hybrid cache architecture with disparate memory technologies.
ISCA 2009: 34-45 |
| 9 | | Guangyu Sun,
Xiaoxia Wu,
Yuan Xie:
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.
ISLPED 2009: 295-298 |
| 8 | | Xiaoxia Wu,
Paul Falkenstern,
Krishnendu Chakrabarty,
Yuan Xie:
Scan-chain design and optimization for three-dimensional integrated circuits.
JETC 5(2): (2009) |
| 2008 |
|---|
| 7 | | Feng Wang,
Xiaoxia Wu,
Yuan Xie:
Variability-driven module selection with joint design time optimization and post-silicon tuning.
ASP-DAC 2008: 2-9 |
| 6 | | Xiangyu Dong,
Xiaoxia Wu,
Guangyu Sun,
Yuan Xie,
Helen Li,
Yiran Chen:
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.
DAC 2008: 554-559 |
| 5 | | Krishnan Ramakrishnan,
Xiaoxia Wu,
Narayanan Vijaykrishnan,
Yuan Xie:
Comparative analysis of NBTI effects on low power and high performance flip-flops.
ICCD 2008: 200-205 |
| 4 | | Xiaoxia Wu,
Yibo Chen,
Krishnendu Chakrabarty,
Yuan Xie:
Test-access mechanism optimization for core-based three-dimensional SOCs.
ICCD 2008: 212-218 |
| 2007 |
|---|
| 3 | | Feng Wang,
Chrysostomos Nicopoulos,
Xiaoxia Wu,
Yuan Xie,
Narayanan Vijaykrishnan:
Variation-aware task allocation and scheduling for MPSoC.
ICCAD 2007: 598-603 |
| 2 | | Xiaoxia Wu,
Paul Falkenstern,
Yuan Xie:
Scan chain design for three-dimensional integrated circuits (3D ICs).
ICCD 2007: 208-214 |
| 2006 |
|---|
| 1 | | Wei-Lun Hung,
Xiaoxia Wu,
Yuan Xie:
Guaranteeing performance yield in high-level synthesis.
ICCAD 2006: 303-309 |
