Xunwei Wu Coauthor index DBLP Vis pubzone.org

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DBLP keys2003
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYinshui Xia, Xunwei Wu, A. E. A. Almaini: Power Minimization of FPRM Functions Based on Polarity Conversion. J. Comput. Sci. Technol. 18(3): 325-331 (2003)
2002
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYinshui Xia, Xunwei Wu, Penjung Wang: Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics. ISMVL 2002: 156-160
2000
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMassoud Pedram, Xunwei Wu: Analysis of power-clocked CMOS with application to the design of energy-recovery circuits. ASP-DAC 2000: 339-344
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Jian Wei, Massoud Pedram, Qing Wu: Low-power design of sequential circuits using a quasi-synchronous derived clock. ASP-DAC 2000: 345-350
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Massoud Pedram: Low power sequential circuit design by using priority encoding and clock gating. ISLPED 2000: 143-148
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Xuanchang Zhou: Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic. ISMVL 2000: 227-
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Massoud Pedram: Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic. ISMVL 2000: 453-459
1998
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMassoud Pedram, Qing Wu, Xunwei Wu: A New Design for Double Edge Triggered Flip-flops. ASP-DAC 1998: 417-421
1997
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRakesh Mehrotra, Massoud Pedram, Xunwei Wu: Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells. ICCD 1997: 130-135
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Massoud Pedram: Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits. ISMVL 1997: 209-214
1995
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLShoujue Wang, Xunwei Wu, Hongjuan Feng: The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. ISMVL 1995: 178-181
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Xiexiong Chen, Jizhong Shen: Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits. ISMVL 1995: 222-227
1992
2no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu: The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS Circuits. ISMVL 1992: 119-125
1991
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLXunwei Wu, Xiaowei Deng: Theory of Grounded Current Switches and Quatemary IIL Circuits. ISMVL 1991: 210-215

Coauthor Index

1A. E. A. Almaini [14]
2Xiexiong Chen [3]
3Xiaowei Deng [1]
4Hongjuan Feng [4]
5Rakesh Mehrotra [6]
6Massoud Pedram [5] [6] [7] [8] [10] [11] [12]
7Jizhong Shen [3]
8Penjung Wang [13]
9Shoujue Wang [4]
10Jian Wei [11]
11Qing Wu [7] [11]
12Yinshui Xia [13] [14]
13Xuanchang Zhou [9]

Colors in the list of coauthors

Copyright © Fri Nov 13 21:28:18 2009 by Michael Ley (ley@uni-trier.de)