| 2009 | ||
|---|---|---|
| 51 | Zhen Chen, Dong Xiang, Boxue Yin: A power-effective scan architecture using scan flip-flops clustering and post-generation filling. ACM Great Lakes Symposium on VLSI 2009: 517-522 | |
| 50 | Zhen Chen, Boxue Yin, Dong Xiang: Conflict driven scan chain configuration for high transition fault coverage and low test power. ASP-DAC 2009: 666-671 | |
| 49 | Boxue Yin, Dong Xiang, Zhen Chen: New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. VLSI Design 2009: 221-226 | |
| 48 | Dong Xiang, Yueli Zhang, Yi Pan: Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model. IEEE Trans. Computers 58(5): 620-633 (2009) | |
| 2008 | ||
| 47 | Dong Xiang, Qi Wang, Yi Pan: Deadlock-Free Adaptive Routing in 2D Tori with a New Turn Model. ICA3PP 2008: 58-69 | |
| 46 | Dong Xiang, Yi Pan, Qi Wang, Zhen Chen: Deadlock-Free Fully Adaptive Routing in 2-Dimensional Tori Based on New Virtual Network Partitioning Scheme. ICDCS 2008: 454-461 | |
| 45 | Dong Xiang, Qi Wang, Yi Pan: Deadlock-Free Fully Adaptive Routing in Tori Based on a New Virtual Network Partitioning Scheme. ICPP 2008: 612-619 | |
| 44 | Wei Jiang, Dong Xiang: A Compression Framework for Personal Image Used in Mobile RFID System. ICYCS 2008: 769-774 | |
| 43 | Zhizhou Li, Yaxiong Zhao, Yong Cui, Dong Xiang: A Density Adaptive Routing Protocol for Large-Scale Ad Hoc Networks. WCNC 2008: 2597-2602 | |
| 42 | Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara: A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 999-1012 (2008) | |
| 41 | Dong Xiang, Yueli Zhang, Jia-Guang Sun: Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes. Journal of Systems Architecture - Embedded Systems Design 54(12): 1164-1178 (2008) | |
| 40 | Dong Xiang, Mingjing Chen, Jia-Guang Sun: Scan BIST with biased scan test signals. Science in China Series F: Information Sciences 51(7): 881-895 (2008) | |
| 2007 | ||
| 39 | Dong Xiang, Yueli Zhang, Yi Pan, Jie Wu: Deadlock-Free Adaptive Routing in Meshes Based on Cost-Effective Deadlock Avoidance Schemes. ICPP 2007: 41 | |
| 38 | Hui Wang, Dong Xiang, Guanghong Duan, Linxuan Zhang: Assembly planning based on semantic modeling approach. Computers in Industry 58(3): 227-239 (2007) | |
| 37 | Dong Xiang, Mingjing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. IEEE Trans. Computers 56(12): 1619-1628 (2007) | |
| 36 | Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara: Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. IEEE Trans. Computers 56(4): 557-562 (2007) | |
| 2006 | ||
| 35 | Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun: Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. ICCD 2006 | |
| 34 | Hui Wang, Dong Xiang, Guanghong Duan, Jie Song: A Hybrid Heuristic Approach for Disassembly/Recycle Applications. ISDA (1) 2006: 985-995 | |
| 33 | Dong Xiang: Fault-tolerant routing in hypercubes using partial path set-up. Future Generation Comp. Syst. 22(7): 812-819 (2006) | |
| 32 | Dong Xiang, Ai Chen, Jia-Guang Sun: Fault-tolerant multicasting in hypercubes using local safety information. J. Parallel Distrib. Comput. 66(2): 248-256 (2006) | |
| 2005 | ||
| 31 | Dong Xiang, Ming-Jing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. Asian Test Symposium 2005: 126-131 | |
| 30 | Dong Xiang, Kaiwei Li, Hideo Fujiwara: Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. Asian Test Symposium 2005: 318-323 | |
| 29 | Dong Xiang, Jia-Guang Sun, Jie Wu, Krishnaiyan Thulasiraman: Fault-Tolerant Routing in Meshes/Tori Using Planarly Constructed Fault Blocks. ICPP 2005: 577-584 | |
| 28 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara: Improving test effectiveness of scan-based BIST by scan chain partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 916-927 (2005) | |
| 27 | Dong Xiang, Ai Chen, Jiaguang Sun: Fault-tolerant routing and multicasting in hypercubes using a partial path set-up. Parallel Computing 31(3-4): 389-411 (2005) | |
| 2004 | ||
| 26 | Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu: Scan-Based BIST Using an Improved Scan Forest Architecture. Asian Test Symposium 2004: 88-93 | |
| 25 | Monica Benito, Joel Parker, Quan Du, Junyuan Wu, Dong Xiang, Charles M. Perou, James Stephen Marron: Adjustment of systematic microarray data biases. Bioinformatics 20(1): 105-114 (2004) | |
| 24 | Dong Xiang, Janak H. Patel: Partial Scan Design Based on Circuit State Information and Functional Analysis. IEEE Trans. Computers 53(3): 276-287 (2004) | |
| 2003 | ||
| 23 | Jingli Zhou, Dong Xiang, Shengsheng Yu, Lin Zhong, Jian Gu: A Method of Data Assignment on Heterogeneous Disk System. APPT 2003: 162-166 | |
| 22 | Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara: Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. Asian Test Symposium 2003: 12-17 | |
| 21 | Dong Xiang, Shan Gu, Hideo Fujiwara: Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. Asian Test Symposium 2003: 300-305 | |
| 20 | Dong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu: A cost-effective scan architecture for scan testing with non-scan test power and test application cost. DAC 2003: 744-747 | |
| 19 | Dong Xiang, Ai Chen: Partial Path Set up for Fault Tolerant Routing in Hypercubes. IPDPS 2003: 275 | |
| 18 | Dong Xiang, Yi Xu, Hideo Fujiwara: Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. IEEE Trans. Computers 52(8): 1063-1075 (2003) | |
| 17 | Dong Xiang, Ai Chen, Jie Wu: Reliable broadcasting in wormhole-routed hypercube-connected networks using local safety information. IEEE Transactions on Reliability 52(2): 245-256 (2003) | |
| 16 | Dong Xiang, Ai Chen, Jie Wu: Local-Safety-Information-Based Fault-Tolerant Broadcasting in Hypercubes. J. Inf. Sci. Eng. 19(3): 467-478 (2003) | |
| 2002 | ||
| 15 | Dong Xiang, Shan Gu, Hideo Fujiwara: Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. Asian Test Symposium 2002: 86- | |
| 14 | Dong Xiang, Ai Chen, Jie Wu: Fault-Tolerant Broadcasting in Hypercubes via Local Safety Information. ICPADS 2002: 31-36 | |
| 13 | Dong Xiang, Ai Chen: Fault-Tolerant Routing in 2D Tori or Meshes Using Limited-Global-Safety Information. ICPP 2002: 231-238 | |
| 12 | Dong Xiang, Hideo Fujiwara: Handling the pin overhead problem of DFTs for high-quality and at-speed tests. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1105-1113 (2002) | |
| 2001 | ||
| 11 | Dong Xiang, Yi Xu: A Multiple Phase Partial Scan Design Method. Asian Test Symposium 2001: 17-22 | |
| 10 | Dong Xiang, Yi Xu: Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. ICCD 2001: 154-160 | |
| 9 | Wenke Lee, Dong Xiang: Information-Theoretic Measures for Anomaly Detection. IEEE Symposium on Security and Privacy 2001: 130-143 | |
| 8 | Dong Xiang, Yi Xu: Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. VTS 2001: 82-87 | |
| 7 | Dong Xiang: Fault-Tolerant Routing in Hypercube Multicomputers Using Local Safety Information. IEEE Trans. Parallel Distrib. Syst. 12(9): 942-951 (2001) | |
| 6 | Dong Xiang, Ai Chen, Jie Wu: Local-Safety-Information-Based Broadcasting in Hypercube Multicomputers with Node and Link Faults. Journal of Interconnection Networks 2(3): 365-378 (2001) | |
| 2000 | ||
| 5 | Dong Xiang, Yi Xu, Hideo Fujiwara: Non-scan design for testability for synchronous sequential circuits based on conflict analysis. ITC 2000: 520-529 | |
| 1998 | ||
| 4 | Grace Wahba, Xiwu Lin, Fangyu Gao, Dong Xiang, Ronald Klein, Barbara Klein: The Bias-Variance Tradeoff and the Randomized GACV. NIPS 1998: 620-626 | |
| 1996 | ||
| 3 | Dong Xiang, Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel: Partial Scan Design Based on Circuit State Information. DAC 1996: 807-812 | |
| 2 | Dong Xiang, Janak H. Patel: A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. ITC 1996: 548-557 | |
| 1994 | ||
| 1 | Dong Xiang, Dao-zheng Wei: An Optimal Design for Parallel Test Generation Based on Circuit Partitioning. VLSI Design 1994: 297-300 | |