Yuan Xie

Pennsylvania State University

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2008
72EESyed M. Alam, Mike Ignatowski, Yuan Xie: Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI 2008: 1-2
71EEPrasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim: A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398
70EEFeng Wang, Xiaoxia Wu, Yuan Xie: Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC 2008: 2-9
69EEXiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559
68EEFeng Wang, Guangyu Sun, Yuan Xie: A Variation Aware High Level Synthesis Framework. DATE 2008: 1063-1068
67EEK. Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu: Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683
66EESuresh Srinivasan, Ramakrishnan Krishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008)
2007
65EEFeng Wang, Yuan Xie, Hai Ju: A novel criticality computation method in statistical timing analysis. DATE 2007: 1611-1616
64EEYu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. DATE 2007: 546-551
63EEFeng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603
62EESuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157
61EEXiaoxia Wu, Paul Falkenstern, Yuan Xie: Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD 2007: 208-214
60EEJongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149
59EEHong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Modeling of PMOS NBTI Effect Considering Temperature Variation. ISQED 2007: 139-144
58EEAmol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338
57EEK. Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916
56EEHong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. PATMOS 2007: 160-170
55EEBalaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108
54EEFeng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan: Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design 2007: 165-170
53EEWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems CoRR abs/0710.4660: (2007)
52EESuleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis CoRR abs/0710.4684: (2007)
51EEYuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network CoRR abs/0710.4731: (2007)
50EEGabriel H. Loh, Yuan Xie, Bryan Black: Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007)
49EEChang Hong Lin, Yuan Xie, Wayne Wolf: Code Compression for VLIW Embedded Systems Using a Self-Generating Table. IEEE Trans. VLSI Syst. 15(10): 1160-1171 (2007)
48EEYuan Xie, Wayne Wolf, Haris Lekatsas: Code Decompression Unit Design for VLIW Embedded Processors. IEEE Trans. VLSI Syst. 15(8): 975-980 (2007)
47EEYuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-aware Co-synthesis for Embedded Systems. VLSI Signal Processing 49(1): 87-99 (2007)
2006
46EEBalaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963
45EEOzcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie: Optimal topology exploration for application-specific 3D architectures. ASP-DAC 2006: 390-395
44EESuresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635
43EEFeng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimization. DATE 2006: 850-855
42EEWei-Lun Hung, Xiaoxia Wu, Yuan Xie: Guaranteeing performance yield in high-level synthesis. ICCAD 2006: 303-309
41EEFeihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141
40EEWei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104
39EEShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348
38EEMadhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360
37EEFeng Wang, Yuan Xie, Kerry Bernstein, Yan Luo: Dependability Analysis of Nano-scale FinFET circuits. ISVLSI 2006: 399-404
36EER. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502
35EEThomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664
34EENarayanan Vijaykrishnan, Yuan Xie: Reliability Concerns in Embedded System Designs. IEEE Computer 39(1): 118-120 (2006)
33EEYuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. IEEE Trans. VLSI Syst. 14(5): 525-536 (2006)
32EEYuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein: Design space exploration for 3D architectures. JETC 2(2): 65-103 (2006)
31EEYuan Xie, Wei-Lun Hung: Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. VLSI Signal Processing 45(3): 177-189 (2006)
2005
30EENarayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1
29EEShengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie: Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544
28EEJohn Conner, Yuan Xie, Mahmut T. Kandemir, Robert Dick, Greg M. Link: FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC 2005: 709-712
27EESuleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263
26EEYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231
25EEShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69
24EEWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899
23EEYuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524
22EESri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie: Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. ICCD 2005: 677-682
21EEWei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696
20EESuleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369
19EESuleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380
18EEWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin: Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639
17EEDaniel Hostetler, Yuan Xie: Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. ISVLSI 2005: 186-191
16EEShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang: Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170
15EEYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379
2004
14EEWei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303
13EEYuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50
12EEChang Hong Lin, Yuan Xie, Wayne Wolf: LZW-Based Code Compression for VLIW Embedded Systems. DATE 2004: 76-81
11EESuresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110
10EEWei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437
9EEVijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508
2003
8EEYuan Xie, Wayne Wolf, Haris Lekatsas: Profile-Driven Selective Code Compression. DATE 2003: 10462-10467
7EEYuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. DCC 2003: 382-391
6EEYuan Xie, Jiang Xu, Wayne Wolf: Augmenting Platform-Based Design with Synthesis Tools. Journal of Circuits, Systems, and Computers 12(2): 125-142 (2003)
2002
5EEHaris Lekatsas, Wayne Wolf, Yuan Xie: Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ISSS 2002: 138-143
2001
4EEYuan Xie, Wayne Wolf: Allocation and scheduling of conditional task graph in hardware/software co-synthesis. DATE 2001: 620-625
3EEYuan Xie, Haris Lekatsas, Wayne Wolf: Code Compression for VLIW Processors. Data Compression Conference 2001: 525
2EEYuan Xie, Wayne Wolf, Haris Lekatsas: A code decompression architecture for VLIW processors. MICRO 2001: 66-75
2000
1EEYuan Xie, Wayne Wolf: Co-synthesis with custom ASICs. ASP-DAC 2000: 129-134

Coauthor Index

1Charles Addo-Quaye [10] [18]
2Syed M. Alam [72]
3Ercument Arvas [19] [20] [27] [52]
4Kerry Bernstein [32] [37]
5Bryan Black [32] [50]
6Guilin Chen [22]
7Yiran Chen [69]
8John Conner [21] [28]
9Chita R. Das [35] [60]
10Reetuparna Das [60]
11Vijay Degalahal [9] [35]
12Nagu R. Dhanwada [21]
13Robert Dick [28]
14Xiangyu Dong [69]
15Melvin Eze [38]
16Paul Falkenstern [61]
17Aman Gayasen [11]
18Ku He [56] [59] [64]
19Daniel Hostetler [17]
20Wei-Lun Hung [10] [18] [19] [20] [21] [24] [31] [40] [42] [53] [55]
21Mike Ignatowski [72]
22Mary Jane Irwin [9] [10] [11] [13] [14] [15] [18] [23] [24] [26] [30] [36] [40] [43] [47] [51] [53] [55] [57] [58] [66] [67] [71]
23Hai Ju [65]
24Mahmut T. Kandemir [11] [13] [19] [20] [22] [24] [27] [28] [41] [45] [47] [52] [53]
25Osama Awadel Karim [71]
26J. S. Kim [36]
27Jongman Kim [60]
28Ramakrishnan Krishnan [66]
29Haris Lekatsas [2] [3] [5] [7] [8] [33] [48]
30Feihui Li [41]
31Helen Li [69]
32Lin Li [13] [47]
33Chang Hong Lin [12] [49]
34Greg M. Link [21] [28] [40]
35Gabriel H. Loh [32] [50]
36Hong Luo [56] [59] [64]
37Rong Luo [46] [56] [59] [64]
38Yan Luo [37]
39Prasanth Mangalagiri [44] [62] [66] [71]
40Nazanin Mansouri [19] [20] [27] [52]
41Amol Mupid [58]
42Madhu Mutyam [38] [58]
43Sri Hari Krishna Narayanan [22]
44Chrysostomos Nicopoulos [35] [41] [60] [63]
45Ozcan Ozturk [20] [45]
46Dongkook Park [35] [60]
47R. Rajaraman [36] [54] [57] [67]
48K. Ramakrishnan [57] [67]
49R. Ramanarayanan [9]
50Thomas D. Richardson [35] [41]
51Karthik Sarpatwari [44] [66] [71]
52Dimitrios N. Serpanos [25]
53Suresh Srinivasan [11] [44] [46] [62] [66]
54Guangyu Sun [68] [69]
55S. Suresh [57]
56Theo Theocharides [10] [18]
57Suleyman Tosun [19] [20] [27] [52]
58Yuh-Fang Tsai [15] [23] [26] [51]
59K. Unlu [67]
60Balaji Vaidyanathan [46] [54] [55]
61Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [9] [10] [11] [13] [14] [15] [16] [18] [21] [23] [24] [25] [26] [29] [30] [34] [35] [36] [38] [39] [40] [41] [43] [44] [46] [47] [51] [53] [55] [57] [58] [60] [62] [63] [66] [67] [71]
62Wenping Wang [16] [29]
63Yu Wang [56] [59] [64]
64Feng Wang [37] [43] [45] [54] [55] [63] [65] [68] [70]
65Wayne Wolf [1] [2] [3] [4] [5] [6] [7] [8] [12] [16] [25] [29] [33] [39] [48] [49]
66Xiaoxia Wu [42] [61] [63] [69] [70]
67Jiang Xu [6]
68Wei Xu [14]
69Aditya Yanamandra [71]
70Huazhong Yang [56] [59] [64]
71Shengqi Yang [16] [25] [29] [39]
72Mazin S. Yousif [60]

Colors in the list of coauthors

Copyright © Fri Oct 3 18:41:27 2008 by Michael Ley (ley@uni-trier.de)