Gefu Xu

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2007

5 Gefu Xu, Adit D. Singh: Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design 2007: 763-768

2006

4 Gefu Xu, Adit D. Singh: Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. European Test Symposium 2006: 9-14

3 Adit D. Singh, Gefu Xu: Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS 2006: 349-357

2005

2 Haihua Yan, Adit D. Singh, Gefu Xu: Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium 2005: 8-13

1 Haihua Yan, Gefu Xu, Adit D. Singh: Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED 2005: 316-320

	2007
5		Gefu Xu, Adit D. Singh: Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design 2007: 763-768
	2006
4		Gefu Xu, Adit D. Singh: Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. European Test Symposium 2006: 9-14
3		Adit D. Singh, Gefu Xu: Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS 2006: 349-357
	2005
2		Haihua Yan, Adit D. Singh, Gefu Xu: Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium 2005: 8-13
1		Haihua Yan, Gefu Xu, Adit D. Singh: Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED 2005: 316-320

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