 | 2009 |
|---|
| 41 |       | Xiao Liu,
Qiang Xu:
Interconnection fabric design for tracing signals in post-silicon validation.
DAC 2009: 352-357 |
| 40 | | Feng Yuan,
Qiang Xu:
On systematic illegal state identification for pseudo-functional testing.
DAC 2009: 702-707 |
| 39 | | Xiao Liu,
Qiang Xu:
Trace signal selection for visibility enhancement in post-silicon validation.
DATE 2009: 1338-1343 |
| 38 | | Xiao Liu,
Qiang Xu:
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment.
DATE 2009: 1494-1499 |
| 37 | | Li Jiang,
Lin Huang,
Qiang Xu:
Test architecture design and optimization for three-dimensional SoCs.
DATE 2009: 220-225 |
| 36 | | Lin Huang,
Feng Yuan,
Qiang Xu:
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms.
DATE 2009: 51-56 |
| 35 | | Qiang Xu,
Yubin Zhang,
Krishnendu Chakrabarty:
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2008 |
|---|
| 34 | | Shan Tang,
Qiang Xu:
A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems.
ASP-DAC 2008: 416-421 |
| 33 | | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
On reducing both shift and capture power for scan-based testing.
ASP-DAC 2008: 653-658 |
| 32 | | Lin Huang,
Feng Yuan,
Qiang Xu:
On reliable modular testing with vulnerable test access mechanisms.
DAC 2008: 834-839 |
| 31 | | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.
DATE 2008: 1184-1189 |
| 30 | | Shan Tang,
Qiang Xu:
In-band Cross-Trigger Event Transmission for Transaction-Based Debug.
DATE 2008: 414-419 |
| 29 | | Feng Yuan,
Lin Huang,
Qiang Xu:
Re-Examining the Use of Network-on-Chip as Test Access Mechanism.
DATE 2008: 808-811 |
| 28 | | Lei Zhang,
Yinhe Han,
Qiang Xu,
Xiaowei Li:
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
DATE 2008: 891-896 |
| 27 | | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.
DELTA 2008: 26-31 |
| 26 | | Qiang Xu,
Jaspal Subhlok:
Construction and Evaluation of Coordinated Performance Skeletons.
HiPC 2008: 73-86 |
| 25 | | Jia Li,
Xiao Liu,
Yubin Zhang,
Yu Hu,
Xiaowei Li,
Qiang Xu:
On capture power-aware test data compression for scan-based testing.
ICCAD 2008: 67-72 |
| 24 |  | Jaspal Subhlok,
Qiang Xu:
Automatic construction of coordinated performance skeletons.
IPDPS 2008: 1-5 |
| 23 | | Lin Huang,
Qiang Xu:
On Modeling the Lifetime Reliability of Homogeneous Manycore Systems.
PRDC 2008: 87-94 |
| 22 | | Sukhdeep Sodhi,
Jaspal Subhlok,
Qiang Xu:
Performance prediction with skeletons.
Cluster Computing 11(2): 151-165 (2008) |
| 21 | | Jing-Ling Yang,
Qiang Xu:
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1338-1343 (2008) |
| 2007 |
|---|
| 20 | | Qiang Xu,
Yubin Zhang,
Krishnendu Chakrabarty:
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.
DAC 2007: 676-681 |
| 19 | | Shan Tang,
Qiang Xu:
A multi-core debug platform for NoC-based systems.
DATE 2007: 870-875 |
| 18 | | Xiucheng Dong,
Haibin Wang,
Qiang Xu,
Xiaoxiao Zhao:
Research on Applications of a New-Type Fuzzy-Neural Network Controller.
LSMS (1) 2007: 679-687 |
| 17 | | Qiang Xu,
Nicola Nicolici,
Krishnendu Chakrabarty:
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007) |
| 2006 |
|---|
| 16 | | Qiang Xu,
Baosheng Wang,
F. Y. Young:
Retention-Aware Test Scheduling for BISTed Embedded SRAMs.
European Test Symposium 2006: 83-88 |
| 15 | | Qiang Xu,
Nicola Nicolici:
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs.
IEEE Trans. Computers 55(4): 470-485 (2006) |
| 14 | | Qiang Xu,
Nicola Nicolici:
Multifrequency TAM design for hierarchical SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 181-196 (2006) |
| 2005 |
|---|
| 13 | | Ho Fai Ko,
Qiang Xu,
Nicola Nicolici:
Register-transfer level functional scan for hierarchical designs.
ASP-DAC 2005: 1172-1175 |
| 12 | | Qiang Xu,
Nicola Nicolici,
Krishnendu Chakrabarty:
Multi-frequency wrapper design and optimization for embedded cores under average power constraints.
DAC 2005: 123-128 |
| 11 | | Qiang Xu,
Jaspal Subhlok:
Automatic clustering of grid nodes.
GRID 2005: 227-233 |
| 10 | | Qiang Xu,
Nicola Nicolici:
Modular and rapid testing of SOCs with unwrapped logic blocks.
IEEE Trans. VLSI Syst. 13(11): 1275-1285 (2005) |
| 9 | | Qiang Xu,
Nicola Nicolici:
Wrapper design for multifrequency IP cores.
IEEE Trans. VLSI Syst. 13(6): 678-685 (2005) |
| 8 | | Qiang Xu,
Nicola Nicolici:
Modular SOC testing with reduced wrapper count.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1894-1908 (2005) |
| 2004 |
|---|
| 7 | | Qiang Xu,
Nicola Nicolici:
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing.
Asian Test Symposium 2004: 2-7 |
| 6 | | Qiang Xu,
Nicola Nicolici:
Wrapper Design for Testing IP Cores with Multiple Clock Domains.
DATE 2004: 416-421 |
| 5 | | Qiang Xu:
Content Management and Resources Integration: A Practice in Shanghai Digital Library.
ICADL 2004: 25-34 |
| 4 | | Qiang Xu,
Nicola Nicolici:
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores.
ITC 2004: 1196-1202 |
| 2003 |
|---|
| 3 | | Qiang Xu,
Nicola Nicolici:
Delay Fault Testing of Core-Based Systems-on-a-Chi.
DATE 2003: 10744-10752 |
| 2 | | Bai Hong Fang,
Qiang Xu,
Nicola Nicolici:
Hardware/Software Co-testing of Embedded Memories in Complex SOCs.
ICCAD 2003: 599-606 |
| 1 | | Qiang Xu,
Nicola Nicolici:
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.
ITC 2003: 622-631 |
