Jingling Xue

薛京灵

	2010
76		Lin Gao, Jingling Xue, Tin-Fook Ngai: Loop recreation for thread-level speculation on multicore processors. Softw., Pract. Exper. 40(1): 45-72 (2010)
	2009
75		Yi Lu, John Potter, Jingling Xue: Ownership Downgrading for Ownership Types. APLAS 2009: 144-160
74		Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue: Optimal loop parallelization for maximizing iteration-level parallelism. CASES 2009: 67-76
73		Lin Gao, Lian Li, Jingling Xue, Tin-Fook Ngai: Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. CC 2009: 78-93
72		Xuejun Yang, Li Wang, Jingling Xue, Yu Deng, Ying Zhang: Comparability graph coloring for optimizing utilization of stream register files in stream processors. PPOPP 2009: 111-120
71		Lian Li, Hui Feng, Jingling Xue: Compiler-directed scratchpad memory management via graph coloring. TACO 6(3): (2009)
	2008
70		Anderson Kuei-An Ku, Jenny Yi-Chun Kuo, Jingling Xue: Hardware Support for Efficient Sparse Matrix Vector Multiplication. EUC (1) 2008: 37-43
69		Lin Gao, Quan Hoang Nguyen, Lian Li, Jingling Xue, Tin-Fook Ngai: Thread-Sensitive Modulo Scheduling for Multicore Processors. ICPP 2008: 132-140
68		Li Wang, Xuejun Yang, Jingling Xue, Yu Deng, Xiaobo Yan, Tao Tang, Quan Hoang Nguyen: Optimizing scientific application loops on stream processors. LCTES 2008: 161-170
67		Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang: Exploiting loop-dependent stream reuse for stream processors. PACT 2008: 22-31
66		Bernhard Scholz, Bernd Burgstaller, Jingling Xue: Minimal placement of bank selection instructions for partitioned memory architectures. ACM Trans. Embedded Comput. Syst. 7(2): (2008)
65		Minyi Guo, Jingling Xue: Advances in high performance computing. The Journal of Supercomputing 43(2): 105-106 (2008)
64		Jingling Xue, Minyi Guo, Daming Wei: Improving the parallelism of iterative methods by aggressive loop fusion. The Journal of Supercomputing 43(2): 147-164 (2008)
	2007
63		Lian Li, Hui Wu, Hui Feng, Jingling Xue: Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. Asia-Pacific Computer Systems Architecture Conference 2007: 63-74
62		Yi Lu, John Potter, Jingling Xue: Validity Invariants and Effects. ECOOP 2007: 202-226
61		Lin Gao, Lian Li, Jingling Xue, Tin-Fook Ngai: Loop recreation for thread-level speculation. ICPADS 2007: 1-10
60		Lei Pan, Jingling Xue, Ming Kin Lai, Michael B. Dillencourt, Lubomir F. Bic: Toward Automatic Data Distribution for Migrating Computations. ICPP 2007: 27
59		Lian Li, Quan Hoang Nguyen, Jingling Xue: Scratchpad allocation for data aggregates in superperfect graphs. LCTES 2007: 207-216
58		Xavier Vera, Björn Lisper, Jingling Xue: Data cache locking for tight timing calculations. ACM Trans. Embedded Comput. Syst. 7(1): (2007)
57		Lian Li, Jingling Xue: Trace-based leakage energy optimisations at link time. Journal of Systems Architecture 53(1): 1-20 (2007)
56		Jingling Xue, Phung Hua Nguyen, John Potter: Interprocedural side-effect analysis for incomplete object-oriented software modules. Journal of Systems and Software 80(1): 92-105 (2007)
	2006
55		Lian Li, Jingling Xue: Trace-Based Data Cache Leakage Reduction at Link Time. Asia-Pacific Computer Systems Architecture Conference 2006: 175-188
54		Bernhard Scholz, Bernd Burgstaller, Jingling Xue: Minimizing bank selection instructions for partitioned memory architecture. CASES 2006: 201-211
53		Jingling Xue, Jens Knoop: A Fresh Look at PRE as a Maximum Flow Problem. CC 2006: 139-154
52		Baoliu Ye, Minyi Guo, Jingling Xue: CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks. ICPP 2006: 577-584
51		Hui Wu, Joxan Jaffar, Jingling Xue: Instruction Scheduling with Release Times and Deadlines on ILP Processors. RTCSA 2006: 51-60
50		Jingling Xue, Qiong Cai, Lin Gao: Partial dead code elimination on predicated code regions. Softw., Pract. Exper. 36(15): 1655-1685 (2006)
49		Jingling Xue, Qiong Cai: A lifetime optimal algorithm for speculative PRE. TACO 3(2): 115-155 (2006)
	2005
48		Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings Springer 2005
47		Phung Hua Nguyen, Jingling Xue: Interprocedural Side-Effect Analysis and Optimisation in the Presence of Dynamic Class Loading. ACSC 2005: 9-18
46		Canqun Yang, Xuejun Yang, Jingling Xue: Improving the Performance of GCC by Exploiting IA-64 Architectural Features. Asia-Pacific Computer Systems Architecture Conference 2005: 236-251
45		Jingling Xue, Phung Hua Nguyen: Completeness Analysis for Incomplete Object-Oriented Programs. CC 2005: 271-286
44		Jingling Xue: Compiler-Directed Scratchpad Memory Management. ICESS 2005: 2
43		Weng-Long Chang, Michael (Shan-Hui) Ho, Minyi Guo, Xiaohong Jiang, Jingling Xue, Minglu Li: Fast Parallel DNA-Based Algorithms for Molecular Computation: Determining a Prime Number. ICITA (1) 2005: 447-452
42		Jingling Xue, Qingguang Huang, Minyi Guo: Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. ICPP 2005: 107-115
41		Lian Li, Lin Gao, Jingling Xue: Memory Coloring: A Compiler Approach for Scratchpad Memory Management. IEEE PACT 2005: 329-338
40		Jingling Xue: Aggressive Loop Fusion for Improving Locality and Parallelism. ISPA 2005: 224-238
39		Pen-Chung Yew, Jingling Xue: Forword. J. Comput. Sci. Technol. 20(5): 575-576 (2005)
38		Jingling Xue: Cache exploitation in embedded systems. J. Embedded Computing 1(4): 435-436 (2005)
	2004
37		Pen-Chung Yew, Jingling Xue: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings Springer 2004
36		Phung Hua Nguyen, Jingling Xue: Strength Reduction for Loop-Invariant Types. ACSC 2004: 213-222
35		Budi Kurniawan, Jingling Xue: A Comparative Study of Web Application Design Models Using the Java Technologies. APWeb 2004: 711-721
34		Qiong Cai, Lin Gao, Jingling Xue: Region-Based Partial Dead Code Elimination on Predicated Code. CC 2004: 150-166
33		Lian Li, Jingling Xue: A trace-based binary compilation framework for energy-aware computing. LCTES 2004: 95-106
32		Jingling Xue, Xavier Vera: Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior. IEEE Trans. Computers 53(5): 547-566 (2004)
	2003
31		Qiong Cai, Jingling Xue: Optimal and Efficient Speculation-Based Partial Redundancy Elimination. CGO 2003: 91-104
30		Qingguang Huang, Jingling Xue, Xavier Vera: Code Tiling for Improving the Cache Performance of PDE Solvers. ICPP 2003: 615-
29		Xavier Vera, Björn Lisper, Jingling Xue: Data Caches in Multitasking Hard Real-Time Systems. RTSS 2003: 154-165
28		Xavier Vera, Björn Lisper, Jingling Xue: Data cache locking for higher program predictability. SIGMETRICS 2003: 272-282
	2002
27		Xavier Vera, Jingling Xue: Let's Study Whole-Program Cache Behaviour Analytically. HPCA 2002: 175-186
26		Jingling Xue, Patrick M. Lenders: Space-Time Equations for Non-Unimodular Mappings. Int. J. Comput. Math. 79(5): 555 (2002)
25		Patrick M. Lenders, Jingling Xue: Eigenvectors-based parallelisation of nested loops with affine dependences. Parallel Algorithms Appl. 17(3): 227-248 (2002)
24		Jingling Xue, Wentong Cai: Time-minimal tiling when rise is larger than zero. Parallel Computing 28(6): 915-939 (2002)
	2000
23		Jingling Xue: Loop Tiling for Parallelism Kluwer 2000
22		Peiyi Tang, Jingling Xue: Generating efficient tiled code for distributed memory machines. Parallel Computing 26(11): 1369-1410 (2000)
	1999
21		Shiping Chen, Jingling Xue: Partitioning and scheduling loops on NOWs. Computer Communications 22(11): 1017-1033 (1999)
	1998
20		Jingling Xue, Chua-Huang Huang: Reuse-Driven Tiling for Improving Data Locality. International Journal of Parallel Programming 26(6): 671-696 (1998)
	1997
19		Jingling Xue, Chua-Huang Huang: Reuse-Driven Tiling for Data Locality. LCPC 1997: 16-33
18		Jingling Xue: Communication-Minimal Tiling of Uniform Dependence Loops. J. Parallel Distrib. Comput. 42(1): 42-59 (1997)
17		Jingling Xue: Unimodular Transformations of Non-Perfectly Nested Loops. Parallel Computing 22(12): 1621-1645 (1997)
16		Jingling Xue: On Tiling as a Loop Transformation. Parallel Processing Letters 7(4): 409-424 (1997)
	1996
15		Jingling Xue: Affine-by-Statement Transformations of Imperfectly Nested Loops. IPPS 1996: 34-38
14		Jingling Xue: Communication-Minimal Tiling of Uniform Dependence Loops. LCPC 1996: 330-349
13		Jingling Xue: Transformations of Nested Loops with Non-Convex Iteration Spaces. Parallel Computing 22(3): 339-368 (1996)
12		Jingling Xue: Generalising the Unimodular Approach to Restructure Imperfectly Nested Loops. Parallel Processing Letters 6(3): 401-414 (1996)
	1995
11		Jingling Xue: Constructing DO loops for non-convex iteration spaces in compiling for parallel machines. IPPS 1995: 364-368
10		Jingling Xue: Closed-form mapping conditions for the synthesis of linear processor arrays. VLSI Signal Processing 10(2): 181-199 (1995)
	1994
9		Jingling Xue, Patrick M. Lenders: Avoiding Data Link and Computational Conflicts in Mapping Nested Loop Algorithms to Lower-Dimensional Processor Arrays. ICPADS 1994: 567-572
8		Jingling Xue: Automating Non-Unimodular Loop Transformations for Massive Parallelism. Parallel Computing 20(5): 711-728 (1994)
	1993
7		Jingling Xue: An Algorithm to Automate Non-Unimodular Transformations of Loop Nests. SPDP 1993: 512-521
	1992
6		Jingling Xue: On the Loading, Recovery and Access of Stationary Data in Systolic Arrays. CONPAR 1992: 259-264
5		Christian Lengauer, Jingling Xue: A systolic array for pyramidal algorithms. VLSI Signal Processing 4(1): 89 (1992)
	1991
4		Jingling Xue, Christian Lengauer: Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. Algorithms and Parallel VLSI Architectures 1991: 181-186
3		Jingling Xue: Specifying control signals for Systolic Arrays by Uniform Recurrence Equations. Parallel Processing Letters 1: 83-93 (1991)
2		Christian Lengauer, Jingling Xue: A systolic array for pyramidal algorithms. VLSI Signal Processing 3(3): 237-257 (1991)
	1988
1		Jingling Xue, Xian-Long Hong: A new data structure for representing cell hierarchy in layout design. Computers & Graphics 12(3-4): 341-348 (1988)

Coauthor Index

1	Lubomir F. Bic (Lubomir Bic)	[60]
2	Bernd Burgstaller	[54] [66]
3	Qiong Cai	[31] [34] [49] [50]
4	Wentong Cai	[24]
5	Chip-Hong Chang	[48]
6	Weng-Long Chang	[43]
7	Shiping Chen	[21]
8	Yu Deng	[68] [72]
9	Michael B. Dillencourt	[60]
10	Hui Feng	[63] [71]
11	Lin Gao	[34] [41] [50] [61] [69] [73] [76]
12	Minyi Guo	[42] [43] [52] [64] [65] [74]
13	Michael (Shan-Hui) Ho	[43]
14	Xian-Long Hong	[1]
15	Chua-Huang Huang	[19] [20]
16	Qingguang Huang	[30] [42]
17	Joxan Jaffar	[51]
18	Xiaohong Jiang	[43]
19	Jens Knoop	[53]
20	Anderson Kuei-An Ku	[70]
21	Jenny Yi-Chun Kuo	[70]
22	Budi Kurniawan	[35]
23	Ming Kin Lai	[60]
24	Patrick M. Lenders	[9] [25] [26]
25	Christian Lengauer	[2] [4] [5]
26	Gen Li	[67]
27	Minglu Li	[43]
28	Lian Li	[33] [41] [55] [57] [59] [61] [63] [69] [71] [73]
29	Björn Lisper	[28] [29] [58]
30	Duo Liu	[74]
31	Yi Lu	[62] [75]
32	Tin-Fook Ngai	[61] [69] [73] [76]
33	Phung Hua Nguyen	[36] [45] [47] [56]
34	Quan Hoang Nguyen	[59] [68] [69]
35	Lei Pan	[60]
36	John Potter	[56] [62] [75]
37	Ian Rogers	[67]
38	Bernhard Scholz	[54] [66]
39	Zili Shao	[74]
40	Thambipillai Srikanthan	[48]
41	Peiyi Tang	[22]
42	Tao Tang	[68]
43	Xavier Vera	[27] [28] [29] [30] [32] [58]
44	Guibin Wang	[67]
45	Li Wang	[68] [72]
46	Meng Wang	[74]
47	Daming Wei	[64]
48	Hui Wu	[51] [63]
49	Xiaobo Yan	[68]
50	Canqun Yang	[46]
51	Xuejun Yang	[46] [67] [68] [72]
52	Baoliu Ye	[52]
53	Pen-Chung Yew	[37] [39]
54	Ying Zhang	[67] [72]

Colors in the list of coauthors