Yoshinobu Yamagami

	2007
3		Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami: A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. IEICE Transactions 90-C(4): 749-757 (2007)
	2006
2		Hiroyuki Yamauchi, Toshikazu Suzuki, Yoshinobu Yamagami: A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. IEICE Transactions 89-C(11): 1526-1534 (2006)
	2005
1		Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi: 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. IEICE Transactions 88-C(4): 630-638 (2005)

Coauthor Index

1	Hironori Akamatsu	[1]
2	Ichiro Hatanaka	[1]
3	Akinori Shibayama	[1]
4	Toshikazu Suzuki	[1] [2] [3]
5	Hiroyuki Yamauchi	[1] [2] [3]