| 2007 | ||
|---|---|---|
| 2 | Yasue Yamamoto, Masanori Shirahama, Toshiaki Kawasaki, Ryuji Nishihara, Shinichi Sumi, Yasuhiro Agata, Hirohito Kikukawa, Hiroyuki Yamauchi: A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. IEICE Transactions 90-C(5): 1129-1137 (2007) | |
| 2006 | ||
| 1 | Yasue Yamamoto, Takeshi Hidaka, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka: Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering. IEICE Transactions 89-C(4): 560-567 (2006) | |