 | 2005 |
|---|
| 4 |       | Ulkuhan Ekinciel,
Hiroaki Yamaoka,
Hiroaki Yoshida,
Makoto Ikeda,
Kunihiro Asada:
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.
IEICE Transactions 88-D(6): 1159-1167 (2005) |
| 2002 |
|---|
| 3 | | Hiroaki Yoshida,
Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
Logic synthesis for PLA with 2-input logic elements.
ISCAS (3) 2002: 373-376 |
| 2 | | Hiroaki Yoshida,
Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.
VLSI Design 2002: 166-171 |
| 2001 |
|---|
| 1 | | Hiroaki Yamaoka,
Makoto Ikeda,
Kunihiro Asada:
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.
ASP-DAC 2001: 3-4 |
