| 2009 | ||
|---|---|---|
| 38 | Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita: Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size CoRR abs/0908.2468: (2009) | |
| 37 | Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita: Multi-Party Quantum Communication Complexity with Routed Messages. IEICE Transactions 92-D(2): 191-199 (2009) | |
| 2008 | ||
| 36 | Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita: Multi-party Quantum Communication Complexity with Routed Messages. COCOON 2008: 180-190 | |
| 35 | Kazuo Iwama, Harumichi Nishimura, Mike Paterson, Rudy Raymond, Shigeru Yamashita: Polynomial-Time Construction of Linear Network Coding. ICALP (1) 2008: 271-282 | |
| 34 | Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita: Quantum Query Complexity of Boolean Functions with Small On-Sets. ISAAC 2008: 907-918 | |
| 33 | Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller: DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Transactions 91-A(12): 3793-3802 (2008) | |
| 2007 | ||
| 32 | Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima: A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC 2007: 343-349 | |
| 31 | Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita: Unbounded-Error One-Way Classical and Quantum Communication Complexity. ICALP 2007: 110-121 | |
| 30 | Shigeru Yamashita, Masaki Nakanishi: A practical framework to utilize quantum search. IEEE Congress on Evolutionary Computation 2007: 4086-4093 | |
| 29 | Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita: Unbounded-Error Classical and Quantum Communication Complexity. ISAAC 2007: 100-111 | |
| 28 | Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond Harry Putra, Shigeru Yamashita: Quantum Network Coding. STACS 2007: 610-621 | |
| 27 | Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe: Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. IEICE Transactions 90-D(2): 395-402 (2007) | |
| 26 | Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond, Shigeru Yamashita: Improved algorithms for quantum identification of Boolean oracles. Theor. Comput. Sci. 378(1): 41-53 (2007) | |
| 2006 | ||
| 25 | Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi: A transduction-based framework to synthesize RSFQ circuits. ASP-DAC 2006: 266-272 | |
| 24 | Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe: Robust Quantum Algorithms with epsilon-Biased Oracles. COCOON 2006: 116-125 | |
| 23 | Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita: Quantum Network Coding. Complexity of Boolean Functions 2006 | |
| 22 | Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond Harry Putra, Shigeru Yamashita: Improved Algorithms for Quantum Identification of Boolean Oracles. SWAT 2006: 280-291 | |
| 21 | Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe: An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. IEICE Transactions 89-A(12): 3416-3426 (2006) | |
| 20 | Mark Adcock, Richard Cleve, Kazuo Iwama, Raymond H. Putra, Shigeru Yamashita: Quantum lower bounds for the Goldreich-Levin problem. Inf. Process. Lett. 97(5): 208-211 (2006) | |
| 2005 | ||
| 19 | Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita: Event-oriented computing with reconfigurable platform. ASP-DAC 2005: 1248-1251 | |
| 18 | Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe: Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234 | |
| 17 | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi: SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits. IEICE Transactions 88-A(4): 1038-1046 (2005) | |
| 16 | Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita: Quantum Sampling for Balanced Allocations. IEICE Transactions 88-D(1): 39-46 (2005) | |
| 2004 | ||
| 15 | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi: SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. ACM Great Lakes Symposium on VLSI 2004: 348-353 | |
| 14 | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi: SPFD-based one-to-many rewiring. FPGA 2004: 250 | |
| 13 | Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Hiroyuki Masuda, Raymond H. Putra, Shigeru Yamashita: Quantum Identification of Boolean Oracles. STACS 2004: 105-116 | |
| 2003 | ||
| 12 | Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita: Quantum Sampling for Balanced Allocations. COCOON 2003: 304-318 | |
| 11 | Noboru Kunihiro, Shigeru Yamashita: Efficient Algorithms for NMR Quantum Computers with Small Qubits. New Generation Comput. 21(4): (2003) | |
| 10 | Kazuo Iwama, Shigeru Yamashita: Transformation Rules for CNOT-based Quantum Circuits and Their Applications. New Generation Comput. 21(4): (2003) | |
| 2002 | ||
| 9 | Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita: Transformation rules for designing CNOT-based quantum circuits. DAC 2002: 419-424 | |
| 2000 | ||
| 8 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC 2000: 253-258 | |
| 7 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: SPFD: A new method to express functional flexibility. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 840-849 (2000) | |
| 1999 | ||
| 6 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI 1999: 136-139 | |
| 1998 | ||
| 5 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC 1998: 59-68 | |
| 4 | Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya: Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE 1998: 755- | |
| 1997 | ||
| 3 | Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya: Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI 1997: 39-44 | |
| 1996 | ||
| 2 | Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya: A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD 1996: 254-261 | |
| 1995 | ||
| 1 | Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga: Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC 1995 | |